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[2620:137:e000::1:20]) by mx.google.com with ESMTP id i13-20020a633c4d000000b0046ebb8ff289si5640690pgn.112.2022.10.25.20.29.05; Tue, 25 Oct 2022 20:29:17 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b=Z1SZar7W; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232338AbiJZD1r (ORCPT + 99 others); Tue, 25 Oct 2022 23:27:47 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37994 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231544AbiJZD0p (ORCPT ); Tue, 25 Oct 2022 23:26:45 -0400 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5599C6E2F2; Tue, 25 Oct 2022 20:26:44 -0700 (PDT) Received: from pps.filterd (m0279872.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.5/8.17.1.5) with ESMTP id 29Q3GJAu025720; Wed, 26 Oct 2022 03:26:37 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=qcppdkim1; bh=jTPfKjNehpKpThO05qUrptqJYOOOJHuYOX1iBFMDJ28=; b=Z1SZar7Wd5ItqlpF/uKGakreCAOxEmJij5RVa+2ox2yUg8jbERRm+YfLluXBrOQc5Yun MbkbFIJYAgzTcy/I2oLnYQjgqbekIZvT7QSm8u4K6J5fUVz6HTyaElAqUxakXC0VLrqC mTN53k9KpXAOJCtcZEqK6xyGHiOnR0MCH0np9OXoSd3IWMK2bBmS3P+vIWP0XIpcAnG6 1rGbkKZMCUl9bgtYt289vc3UGGud5497b+YB087KCcN9GVvzR7AkC/bHxipPnma6w7iA kEYVvti6FrhZXXY5+RStuVX8gintPNg3mhkQ4U3RFdsJkrp+Fj2g2OCksLbOW0h6W5EQ gw== Received: from nalasppmta02.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3keaf0j8mc-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 26 Oct 2022 03:26:37 +0000 Received: from nalasex01c.na.qualcomm.com (nalasex01c.na.qualcomm.com [10.47.97.35]) by NALASPPMTA02.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 29Q3QajM029681 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 26 Oct 2022 03:26:36 GMT Received: from th-lint-050.qualcomm.com (10.80.80.8) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.29; Tue, 25 Oct 2022 20:26:36 -0700 From: Bjorn Andersson To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov CC: Sean Paul , David Airlie , "Daniel Vetter" , Rob Herring , "Krzysztof Kozlowski" , Bjorn Andersson , Konrad Dybcio , "Kuogee Hsieh" , Sankeerth Billakanti , Johan Hovold , , , , , Subject: [PATCH v3 09/12] drm/msm/dp: HPD handling relates to next_bridge Date: Tue, 25 Oct 2022 20:26:21 -0700 Message-ID: <20221026032624.30871-10-quic_bjorande@quicinc.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20221026032624.30871-1-quic_bjorande@quicinc.com> References: <20221026032624.30871-1-quic_bjorande@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01c.na.qualcomm.com (10.47.97.35) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: _LGyVcTI3ly4dL0T_JIqi2WA6iEPBeiD X-Proofpoint-ORIG-GUID: _LGyVcTI3ly4dL0T_JIqi2WA6iEPBeiD X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.895,Hydra:6.0.545,FMLib:17.11.122.1 definitions=2022-10-25_15,2022-10-25_01,2022-06-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 mlxlogscore=999 priorityscore=1501 suspectscore=0 phishscore=0 spamscore=0 adultscore=0 clxscore=1015 malwarescore=0 lowpriorityscore=0 mlxscore=0 impostorscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2209130000 definitions=main-2210260016 X-Spam-Status: No, score=-2.8 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_LOW,SPF_HELO_NONE, SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1747719246546653460?= X-GMAIL-MSGID: =?utf-8?q?1747719246546653460?= From: Bjorn Andersson The DisplayPort controller's internal HPD interrupt handling is used for cases where the HPD signal is connected to a GPIO which is pinmuxed into the DisplayPort controller. Most of the logic for enabling and disabling the HPD-related interrupts is conditioned on the presence of an EDP panel, but more generically designs that has a downstream drm_bridge (next_bridge) could use this to handle the HPD interrupts, instead of the internal mechanism. So replace the current is_edp-based guards with a check for the presence of next_bridge. Signed-off-by: Bjorn Andersson Signed-off-by: Bjorn Andersson --- Changes since v2: - None drivers/gpu/drm/msm/dp/dp_display.c | 15 +++++++-------- 1 file changed, 7 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/msm/dp/dp_display.c b/drivers/gpu/drm/msm/dp/dp_display.c index 3d365950de0f..224ae3aa07c4 100644 --- a/drivers/gpu/drm/msm/dp/dp_display.c +++ b/drivers/gpu/drm/msm/dp/dp_display.c @@ -610,7 +610,7 @@ static int dp_hpd_plug_handle(struct dp_display_private *dp, u32 data) } /* enable HDP irq_hpd/replug interrupt */ - if (!dp->dp_display.is_edp) + if (!dp->dp_display.next_bridge) dp_catalog_hpd_config_intr(dp->catalog, DP_DP_IRQ_HPD_INT_MASK | DP_DP_HPD_REPLUG_INT_MASK, true); @@ -653,7 +653,7 @@ static int dp_hpd_unplug_handle(struct dp_display_private *dp, u32 data) dp->dp_display.connector_type, state); /* disable irq_hpd/replug interrupts */ - if (!dp->dp_display.is_edp) + if (!dp->dp_display.next_bridge) dp_catalog_hpd_config_intr(dp->catalog, DP_DP_IRQ_HPD_INT_MASK | DP_DP_HPD_REPLUG_INT_MASK, false); @@ -682,7 +682,7 @@ static int dp_hpd_unplug_handle(struct dp_display_private *dp, u32 data) } /* disable HPD plug interrupts */ - if (!dp->dp_display.is_edp) + if (!dp->dp_display.next_bridge) dp_catalog_hpd_config_intr(dp->catalog, DP_DP_HPD_PLUG_INT_MASK, false); /* @@ -701,7 +701,7 @@ static int dp_hpd_unplug_handle(struct dp_display_private *dp, u32 data) dp_display_handle_plugged_change(&dp->dp_display, false); /* enable HDP plug interrupt to prepare for next plugin */ - if (!dp->dp_display.is_edp) + if (!dp->dp_display.next_bridge) dp_catalog_hpd_config_intr(dp->catalog, DP_DP_HPD_PLUG_INT_MASK, true); drm_dbg_dp(dp->drm_dev, "After, type=%d hpd_state=%d\n", @@ -1086,8 +1086,8 @@ static void dp_display_config_hpd(struct dp_display_private *dp) dp_display_host_init(dp); dp_catalog_ctrl_hpd_config(dp->catalog); - /* Enable plug and unplug interrupts only for external DisplayPort */ - if (!dp->dp_display.is_edp) + /* Enable plug and unplug interrupts only if not handled by next_bridge */ + if (!dp->dp_display.next_bridge) dp_catalog_hpd_config_intr(dp->catalog, DP_DP_HPD_PLUG_INT_MASK | DP_DP_HPD_UNPLUG_INT_MASK, @@ -1379,8 +1379,7 @@ static int dp_pm_resume(struct device *dev) dp_catalog_ctrl_hpd_config(dp->catalog); - - if (!dp->dp_display.is_edp) + if (!dp->dp_display.next_bridge) dp_catalog_hpd_config_intr(dp->catalog, DP_DP_HPD_PLUG_INT_MASK | DP_DP_HPD_UNPLUG_INT_MASK,