| Message ID | 20221025182508.10687-1-vidyas@nvidia.com |
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| State | New |
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From: Vidya Sagar <vidyas@nvidia.com>
To: <robh+dt@kernel.org>, <krzysztof.kozlowski+dt@linaro.org>,
<thierry.reding@gmail.com>, <jonathanh@nvidia.com>,
<mperttunen@nvidia.com>
CC: <devicetree@vger.kernel.org>, <linux-tegra@vger.kernel.org>,
<linux-kernel@vger.kernel.org>, <kthota@nvidia.com>,
<mmaddireddy@nvidia.com>, <vidyas@nvidia.com>, <sagar.tv@gmail.com>
Subject: [PATCH] arm64: tegra: Fix non-prefetchable aperture of PCIe C3
controller
Date: Tue, 25 Oct 2022 23:55:08 +0530
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arm64: tegra: Fix non-prefetchable aperture of PCIe C3 controller
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Commit Message
Vidya Sagar
Oct. 25, 2022, 6:25 p.m. UTC
Fix the starting address of the non-prefetchable aperture of PCIe C3
controller.
Fixes: ec142c44b026 ("arm64: tegra: Add P2U and PCIe controller nodes to Tegra234 DT")
Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
---
arch/arm64/boot/dts/nvidia/tegra234.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
Comments
On Tue, Oct 25, 2022 at 11:55:08PM +0530, Vidya Sagar wrote: > Fix the starting address of the non-prefetchable aperture of PCIe C3 > controller. > > Fixes: ec142c44b026 ("arm64: tegra: Add P2U and PCIe controller nodes to Tegra234 DT") > Signed-off-by: Vidya Sagar <vidyas@nvidia.com> > --- > arch/arm64/boot/dts/nvidia/tegra234.dtsi | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) Applied, thanks. Thierry
diff --git a/arch/arm64/boot/dts/nvidia/tegra234.dtsi b/arch/arm64/boot/dts/nvidia/tegra234.dtsi index 5d7df32fd159..85b0dea33117 100644 --- a/arch/arm64/boot/dts/nvidia/tegra234.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra234.dtsi @@ -2343,7 +2343,7 @@ bus-range = <0x0 0xff>; ranges = <0x43000000 0x21 0x00000000 0x21 0x00000000 0x0 0x28000000>, /* prefetchable memory (640 MB) */ - <0x02000000 0x0 0x40000000 0x21 0xe8000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ + <0x02000000 0x0 0x40000000 0x21 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ <0x01000000 0x0 0x34100000 0x00 0x34100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE3R &emc>,