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[2620:137:e000::1:20]) by mx.google.com with ESMTP id gn7-20020a1709070d0700b007833cbbb747si660173ejc.578.2022.10.24.12.25.27; Mon, 24 Oct 2022 12:25:54 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@chromium.org header.s=google header.b=nzykeBNF; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=chromium.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232386AbiJXTXY (ORCPT + 99 others); Mon, 24 Oct 2022 15:23:24 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44570 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232171AbiJXTVv (ORCPT ); Mon, 24 Oct 2022 15:21:51 -0400 Received: from mail-pf1-x431.google.com (mail-pf1-x431.google.com [IPv6:2607:f8b0:4864:20::431]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1650C2D75B for ; Mon, 24 Oct 2022 10:57:14 -0700 (PDT) Received: by mail-pf1-x431.google.com with SMTP id d10so9605406pfh.6 for ; Mon, 24 Oct 2022 10:57:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=kj33p7JdC03bi8muflplwrkkTeKEhU1qK5ms8K2qnYw=; b=nzykeBNFH40raHYAmGXOty01g/6nzbiDvq+zDWKIdNwOAPn5f8q4jxQnDVsAG1oDcC AhM8H5Av+nJ9E6ng/FNVrDq75WbJDwmUEvLj2Kg814cjo2iUn/ASUE04gAbuSFX1lRDy BCKNYIqneKZWIYFdZOXNRu+y0xg7hgX7j7WGY= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=kj33p7JdC03bi8muflplwrkkTeKEhU1qK5ms8K2qnYw=; b=bDCl2Lx2tGwDWSGt4BjSX9Bggi90kHK5YWQGVj6Xdp3/CFQUGsutaeJ6pzmRT5j7oj N+Xuq/ZiXdSQBXGjZRvYtXCglocpAp0rfnh3Dr/6E3xqZ6kHoaW4U80Q1Yr1JcCIACK+ ze9d/Mxqo+wSPJWbrKyYxYu9UsL/KGEYqth9+HEt4TOlhV9KaLaE5JLJAazwfrE/CNr7 POU3ZL6LT9MDdymtMO+eJuMUCezD+GqdwRjztZ96TBHH7Ip4L55xyLIUyF1gwlFN2NsB IW7oJnQRITHNrFisDXOVzePTtrc0MwMQwnmWgJUfhWPPMKcv9SXhp+xC4ldSxsqJn6vI lHKw== X-Gm-Message-State: ACrzQf3wcYCWipNVZb8XJ1tt4NkFa80ipeVDxou/Gwcz5mzJDImpZIUe y5cXEZHP1ilTnO/9wxTkMlLd+A== X-Received: by 2002:a05:6a00:e1b:b0:537:7c74:c405 with SMTP id bq27-20020a056a000e1b00b005377c74c405mr34703121pfb.43.1666634176496; Mon, 24 Oct 2022 10:56:16 -0700 (PDT) Received: from localhost ([2620:15c:9d:2:808b:e2f6:edcf:ccb0]) by smtp.gmail.com with UTF8SMTPSA id a1-20020a170902ecc100b0016cf3f124e1sm30195plh.234.2022.10.24.10.56.14 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 24 Oct 2022 10:56:15 -0700 (PDT) From: Brian Norris To: Ulf Hansson Cc: Shawn Lin , linux-mmc@vger.kernel.org, Al Cooper , Bjorn Andersson , Sowjanya Komatineni , Broadcom internal kernel review list , Sascha Hauer , Konrad Dybcio , Florian Fainelli , NXP Linux Team , Thierry Reding , Fabio Estevam , Michal Simek , linux-kernel@vger.kernel.org, Shawn Guo , Adrian Hunter , Pengutronix Kernel Team , linux-arm-msm@vger.kernel.org, Haibo Chen , Andy Gross , linux-arm-kernel@lists.infradead.org, Faiz Abbas , Jonathan Hunter , Brian Norris , stable@vger.kernel.org, Guenter Roeck Subject: [PATCH v3 2/7] mmc: sdhci-of-arasan: Fix SDHCI_RESET_ALL for CQHCI Date: Mon, 24 Oct 2022 10:54:56 -0700 Message-Id: <20221024105229.v3.2.I29f6a2189e84e35ad89c1833793dca9e36c64297@changeid> X-Mailer: git-send-email 2.38.0.135.g90850a2211-goog In-Reply-To: <20221024175501.2265400-1-briannorris@chromium.org> References: <20221024175501.2265400-1-briannorris@chromium.org> MIME-Version: 1.0 X-Spam-Status: No, score=-2.6 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1747598237554582292?= X-GMAIL-MSGID: =?utf-8?q?1747598237554582292?= SDHCI_RESET_ALL resets will reset the hardware CQE state, but we aren't tracking that properly in software. When out of sync, we may trigger various timeouts. It's not typical to perform resets while CQE is enabled, but one particular case I hit commonly enough: mmc_suspend() -> mmc_power_off(). Typically we will eventually deactivate CQE (cqhci_suspend() -> cqhci_deactivate()), but that's not guaranteed -- in particular, if we perform a partial (e.g., interrupted) system suspend. The same bug was already found and fixed for two other drivers, in v5.7 and v5.9: 5cf583f1fb9c mmc: sdhci-msm: Deactivate CQE during SDHC reset df57d73276b8 mmc: sdhci-pci: Fix SDHCI_RESET_ALL for CQHCI for Intel GLK-based controllers The latter is especially prescient, saying "other drivers using CQHCI might benefit from a similar change, if they also have CQHCI reset by SDHCI_RESET_ALL." So like these other patches, deactivate CQHCI when resetting the controller. Do this via the new sdhci_and_cqhci_reset() helper. Fixes: 84362d79f436 ("mmc: sdhci-of-arasan: Add CQHCI support for arasan,sdhci-5.1") Cc: Signed-off-by: Brian Norris Reviewed-by: Guenter Roeck Acked-by: Adrian Hunter --- Changes in v3: - Refactor to a "SDHCI and CQHCI" helper -- sdhci_and_cqhci_reset() Changes in v2: - Rely on cqhci_deactivate() to safely handle (ignore) not-yet-initialized CQE support drivers/mmc/host/sdhci-of-arasan.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/mmc/host/sdhci-of-arasan.c b/drivers/mmc/host/sdhci-of-arasan.c index 3997cad1f793..cfb891430174 100644 --- a/drivers/mmc/host/sdhci-of-arasan.c +++ b/drivers/mmc/host/sdhci-of-arasan.c @@ -25,6 +25,7 @@ #include #include "cqhci.h" +#include "sdhci-cqhci.h" #include "sdhci-pltfm.h" #define SDHCI_ARASAN_VENDOR_REGISTER 0x78 @@ -366,7 +367,7 @@ static void sdhci_arasan_reset(struct sdhci_host *host, u8 mask) struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host); - sdhci_reset(host, mask); + sdhci_and_cqhci_reset(host, mask); if (sdhci_arasan->quirks & SDHCI_ARASAN_QUIRK_FORCE_CDTEST) { ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);