Message ID | 20221024105229.v3.2.I29f6a2189e84e35ad89c1833793dca9e36c64297@changeid |
---|---|
State | New |
Headers |
Return-Path: <linux-kernel-owner@vger.kernel.org> Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp615239wru; Mon, 24 Oct 2022 12:25:54 -0700 (PDT) X-Google-Smtp-Source: AMsMyM5cj4xwPSrqzpvd5pTPcmAsbe9iH3gEM8pWJHjKMpDqwwrI4NyUHEPvten2bSNqAS3AWuoa X-Received: by 2002:a17:907:7805:b0:780:24fd:c4e8 with SMTP id la5-20020a170907780500b0078024fdc4e8mr29368409ejc.78.1666639554308; Mon, 24 Oct 2022 12:25:54 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1666639554; cv=none; d=google.com; s=arc-20160816; b=yL7i2M12OBUZVuuRY6qXnq4NAsEKFIlTEpaSzGcdsZ1maDPtE3WTHEKpHUeVBE654/ C1Amme7OLonDWu6fJIddzSABpMeUT6SAdBNKr6xtLtjW2gm+wdIbszsvu3+M/4X6oPFw Gb4I4Rx6DsLWl46KVCUYeJSRELQYnrfUeTbp2CYpY9j5G+T0GxHzAolAl9zpqMsQ0n4C Bo3N/36xvBCSVK4t8Gvpn6SrvKlIA973stLnOLLEXL0kNiSR9/uytqCNWTg+ggLnB/cs zlmteIj3Mm0wVLX2fT18GwyOhx42JYAuyBkd4w4eGWyYSI3oPB76evmcGSrZoJANKPpG 1c6g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=kj33p7JdC03bi8muflplwrkkTeKEhU1qK5ms8K2qnYw=; b=cAg/dHHQnxksobA6Chpuvtn10X6fSJms6WJUH6HDBZOfy0lcXoFPc3q5uoF3txKi+1 ZbuusIx/l8P7U2Vq4e9t8gZ2dSxkXB6UpGorpilQuozdfGqsCr4+3A0ckLOal+apMPSq UMeR46ppXehayiJzCMpfpZ9YaB+iF38jsUtC0qZQx6ww61+ynJ9kE6ghmEKHghMwnu7p bmYhhD3vU9alsEz959ceO9Thr67fzX6mi4CDT0L2bxE81Yjid7NjXc701Y9X8WiaOQUe einoyDoa6SfabE/dfN0QjW2AkYy9QOYmNyQ1AZEuae94dYG89S4dhAdRauCblq1Ylu82 3h2w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@chromium.org header.s=google header.b=nzykeBNF; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=chromium.org Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id gn7-20020a1709070d0700b007833cbbb747si660173ejc.578.2022.10.24.12.25.27; Mon, 24 Oct 2022 12:25:54 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@chromium.org header.s=google header.b=nzykeBNF; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=chromium.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232386AbiJXTXY (ORCPT <rfc822;pwkd43@gmail.com> + 99 others); Mon, 24 Oct 2022 15:23:24 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44570 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232171AbiJXTVv (ORCPT <rfc822;linux-kernel@vger.kernel.org>); Mon, 24 Oct 2022 15:21:51 -0400 Received: from mail-pf1-x431.google.com (mail-pf1-x431.google.com [IPv6:2607:f8b0:4864:20::431]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1650C2D75B for <linux-kernel@vger.kernel.org>; Mon, 24 Oct 2022 10:57:14 -0700 (PDT) Received: by mail-pf1-x431.google.com with SMTP id d10so9605406pfh.6 for <linux-kernel@vger.kernel.org>; Mon, 24 Oct 2022 10:57:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=kj33p7JdC03bi8muflplwrkkTeKEhU1qK5ms8K2qnYw=; b=nzykeBNFH40raHYAmGXOty01g/6nzbiDvq+zDWKIdNwOAPn5f8q4jxQnDVsAG1oDcC AhM8H5Av+nJ9E6ng/FNVrDq75WbJDwmUEvLj2Kg814cjo2iUn/ASUE04gAbuSFX1lRDy BCKNYIqneKZWIYFdZOXNRu+y0xg7hgX7j7WGY= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=kj33p7JdC03bi8muflplwrkkTeKEhU1qK5ms8K2qnYw=; b=bDCl2Lx2tGwDWSGt4BjSX9Bggi90kHK5YWQGVj6Xdp3/CFQUGsutaeJ6pzmRT5j7oj N+Xuq/ZiXdSQBXGjZRvYtXCglocpAp0rfnh3Dr/6E3xqZ6kHoaW4U80Q1Yr1JcCIACK+ ze9d/Mxqo+wSPJWbrKyYxYu9UsL/KGEYqth9+HEt4TOlhV9KaLaE5JLJAazwfrE/CNr7 POU3ZL6LT9MDdymtMO+eJuMUCezD+GqdwRjztZ96TBHH7Ip4L55xyLIUyF1gwlFN2NsB IW7oJnQRITHNrFisDXOVzePTtrc0MwMQwnmWgJUfhWPPMKcv9SXhp+xC4ldSxsqJn6vI lHKw== X-Gm-Message-State: ACrzQf3wcYCWipNVZb8XJ1tt4NkFa80ipeVDxou/Gwcz5mzJDImpZIUe y5cXEZHP1ilTnO/9wxTkMlLd+A== X-Received: by 2002:a05:6a00:e1b:b0:537:7c74:c405 with SMTP id bq27-20020a056a000e1b00b005377c74c405mr34703121pfb.43.1666634176496; Mon, 24 Oct 2022 10:56:16 -0700 (PDT) Received: from localhost ([2620:15c:9d:2:808b:e2f6:edcf:ccb0]) by smtp.gmail.com with UTF8SMTPSA id a1-20020a170902ecc100b0016cf3f124e1sm30195plh.234.2022.10.24.10.56.14 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 24 Oct 2022 10:56:15 -0700 (PDT) From: Brian Norris <briannorris@chromium.org> To: Ulf Hansson <ulf.hansson@linaro.org> Cc: Shawn Lin <shawn.lin@rock-chips.com>, linux-mmc@vger.kernel.org, Al Cooper <alcooperx@gmail.com>, Bjorn Andersson <andersson@kernel.org>, Sowjanya Komatineni <skomatineni@nvidia.com>, Broadcom internal kernel review list <bcm-kernel-feedback-list@broadcom.com>, Sascha Hauer <s.hauer@pengutronix.de>, Konrad Dybcio <konrad.dybcio@somainline.org>, Florian Fainelli <f.fainelli@gmail.com>, NXP Linux Team <linux-imx@nxp.com>, Thierry Reding <thierry.reding@gmail.com>, Fabio Estevam <festevam@gmail.com>, Michal Simek <michal.simek@xilinx.com>, linux-kernel@vger.kernel.org, Shawn Guo <shawnguo@kernel.org>, Adrian Hunter <adrian.hunter@intel.com>, Pengutronix Kernel Team <kernel@pengutronix.de>, linux-arm-msm@vger.kernel.org, Haibo Chen <haibo.chen@nxp.com>, Andy Gross <agross@kernel.org>, linux-arm-kernel@lists.infradead.org, Faiz Abbas <faiz_abbas@ti.com>, Jonathan Hunter <jonathanh@nvidia.com>, Brian Norris <briannorris@chromium.org>, stable@vger.kernel.org, Guenter Roeck <linux@roeck-us.net> Subject: [PATCH v3 2/7] mmc: sdhci-of-arasan: Fix SDHCI_RESET_ALL for CQHCI Date: Mon, 24 Oct 2022 10:54:56 -0700 Message-Id: <20221024105229.v3.2.I29f6a2189e84e35ad89c1833793dca9e36c64297@changeid> X-Mailer: git-send-email 2.38.0.135.g90850a2211-goog In-Reply-To: <20221024175501.2265400-1-briannorris@chromium.org> References: <20221024175501.2265400-1-briannorris@chromium.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-2.6 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: <linux-kernel.vger.kernel.org> X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1747598237554582292?= X-GMAIL-MSGID: =?utf-8?q?1747598237554582292?= |
Series |
mmc: sdhci controllers: Fix SDHCI_RESET_ALL for CQHCI
|
|
Commit Message
Brian Norris
Oct. 24, 2022, 5:54 p.m. UTC
SDHCI_RESET_ALL resets will reset the hardware CQE state, but we aren't tracking that properly in software. When out of sync, we may trigger various timeouts. It's not typical to perform resets while CQE is enabled, but one particular case I hit commonly enough: mmc_suspend() -> mmc_power_off(). Typically we will eventually deactivate CQE (cqhci_suspend() -> cqhci_deactivate()), but that's not guaranteed -- in particular, if we perform a partial (e.g., interrupted) system suspend. The same bug was already found and fixed for two other drivers, in v5.7 and v5.9: 5cf583f1fb9c mmc: sdhci-msm: Deactivate CQE during SDHC reset df57d73276b8 mmc: sdhci-pci: Fix SDHCI_RESET_ALL for CQHCI for Intel GLK-based controllers The latter is especially prescient, saying "other drivers using CQHCI might benefit from a similar change, if they also have CQHCI reset by SDHCI_RESET_ALL." So like these other patches, deactivate CQHCI when resetting the controller. Do this via the new sdhci_and_cqhci_reset() helper. Fixes: 84362d79f436 ("mmc: sdhci-of-arasan: Add CQHCI support for arasan,sdhci-5.1") Cc: <stable@vger.kernel.org> Signed-off-by: Brian Norris <briannorris@chromium.org> Reviewed-by: Guenter Roeck <linux@roeck-us.net> --- Changes in v3: - Refactor to a "SDHCI and CQHCI" helper -- sdhci_and_cqhci_reset() Changes in v2: - Rely on cqhci_deactivate() to safely handle (ignore) not-yet-initialized CQE support drivers/mmc/host/sdhci-of-arasan.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-)
Comments
On 24/10/22 20:54, Brian Norris wrote: > SDHCI_RESET_ALL resets will reset the hardware CQE state, but we aren't > tracking that properly in software. When out of sync, we may trigger > various timeouts. > > It's not typical to perform resets while CQE is enabled, but one > particular case I hit commonly enough: mmc_suspend() -> mmc_power_off(). > Typically we will eventually deactivate CQE (cqhci_suspend() -> > cqhci_deactivate()), but that's not guaranteed -- in particular, if > we perform a partial (e.g., interrupted) system suspend. > > The same bug was already found and fixed for two other drivers, in v5.7 > and v5.9: > > 5cf583f1fb9c mmc: sdhci-msm: Deactivate CQE during SDHC reset As checkpatch.pl says: ERROR: Please use git commit description style 'commit <12+ chars of sha1> ("<title line>")' - ie: 'commit 5cf583f1fb9c ("mmc: sdhci-msm: Deactivate CQE during SDHC reset")' > df57d73276b8 mmc: sdhci-pci: Fix SDHCI_RESET_ALL for CQHCI for Intel GLK-based controllers And again > > The latter is especially prescient, saying "other drivers using CQHCI > might benefit from a similar change, if they also have CQHCI reset by > SDHCI_RESET_ALL." > > So like these other patches, deactivate CQHCI when resetting the > controller. Do this via the new sdhci_and_cqhci_reset() helper. For stable, this patch is dependent on "mmc: cqhci: Provide helper for resetting both SDHCI and CQHCI". Best point that out here in this commit message as well. > > Fixes: 84362d79f436 ("mmc: sdhci-of-arasan: Add CQHCI support for arasan,sdhci-5.1") > Cc: <stable@vger.kernel.org> > Signed-off-by: Brian Norris <briannorris@chromium.org> > Reviewed-by: Guenter Roeck <linux@roeck-us.net> Otherwise: Acked-by: Adrian Hunter <adrian.hunter@intel.com> > --- > > Changes in v3: > - Refactor to a "SDHCI and CQHCI" helper -- sdhci_and_cqhci_reset() > > Changes in v2: > - Rely on cqhci_deactivate() to safely handle (ignore) > not-yet-initialized CQE support > > drivers/mmc/host/sdhci-of-arasan.c | 3 ++- > 1 file changed, 2 insertions(+), 1 deletion(-) > > diff --git a/drivers/mmc/host/sdhci-of-arasan.c b/drivers/mmc/host/sdhci-of-arasan.c > index 3997cad1f793..cfb891430174 100644 > --- a/drivers/mmc/host/sdhci-of-arasan.c > +++ b/drivers/mmc/host/sdhci-of-arasan.c > @@ -25,6 +25,7 @@ > #include <linux/firmware/xlnx-zynqmp.h> > > #include "cqhci.h" > +#include "sdhci-cqhci.h" > #include "sdhci-pltfm.h" > > #define SDHCI_ARASAN_VENDOR_REGISTER 0x78 > @@ -366,7 +367,7 @@ static void sdhci_arasan_reset(struct sdhci_host *host, u8 mask) > struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); > struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host); > > - sdhci_reset(host, mask); > + sdhci_and_cqhci_reset(host, mask); > > if (sdhci_arasan->quirks & SDHCI_ARASAN_QUIRK_FORCE_CDTEST) { > ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
diff --git a/drivers/mmc/host/sdhci-of-arasan.c b/drivers/mmc/host/sdhci-of-arasan.c index 3997cad1f793..cfb891430174 100644 --- a/drivers/mmc/host/sdhci-of-arasan.c +++ b/drivers/mmc/host/sdhci-of-arasan.c @@ -25,6 +25,7 @@ #include <linux/firmware/xlnx-zynqmp.h> #include "cqhci.h" +#include "sdhci-cqhci.h" #include "sdhci-pltfm.h" #define SDHCI_ARASAN_VENDOR_REGISTER 0x78 @@ -366,7 +367,7 @@ static void sdhci_arasan_reset(struct sdhci_host *host, u8 mask) struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host); - sdhci_reset(host, mask); + sdhci_and_cqhci_reset(host, mask); if (sdhci_arasan->quirks & SDHCI_ARASAN_QUIRK_FORCE_CDTEST) { ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);