diff mbox series

[V2,01/15] arm64: dts: imx8mp: add mlmix power domain

Message ID 20221024031351.4135651-2-peng.fan@oss.nxp.com
State New
Headers
Series arm64: dts: imx8m-evk: misc dts update |

Commit Message

Peng Fan (OSS) Oct. 24, 2022, 3:13 a.m. UTC 
  From: Peng Fan <peng.fan@nxp.com>

Add mlmix power domain

Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
 arch/arm64/boot/dts/freescale/imx8mp.dtsi | 8 ++++++++
 1 file changed, 8 insertions(+)

Comments

Marco Felsch Oct. 28, 2022, 2:58 p.m. UTC | #1 
On 22-10-24, Peng Fan (OSS) wrote:
> From: Peng Fan <peng.fan@nxp.com>
> 
> Add mlmix power domain
> 
> Signed-off-by: Peng Fan <peng.fan@nxp.com>

Looks good to me, feel free to my:

Acked-by: Marco Felsch <m.felsch@pengutronix.de>

> ---
>  arch/arm64/boot/dts/freescale/imx8mp.dtsi | 8 ++++++++
>  1 file changed, 8 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
> index bb916a0948a8..732a87179edd 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
> @@ -631,6 +631,14 @@ pgc_vpu_vc8000e: power-domain@22 {
>  						reg = <IMX8MP_POWER_DOMAIN_VPU_VC8000E>;
>  						clocks = <&clk IMX8MP_CLK_VPU_VC8KE_ROOT>;
>  					};
> +
> +					pgc_mlmix: power-domain@24 {
> +						#power-domain-cells = <0>;
> +						reg = <IMX8MP_POWER_DOMAIN_MLMIX>;
> +						clocks = <&clk IMX8MP_CLK_ML_AXI>,
> +							 <&clk IMX8MP_CLK_ML_AHB>,
> +							 <&clk IMX8MP_CLK_NPU_ROOT>;
> +					};
>  				};
>  			};
>  		};
> -- 
> 2.37.1
> 
> 
>
diff mbox series

Patch

diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
index bb916a0948a8..732a87179edd 100644
--- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
@@ -631,6 +631,14 @@  pgc_vpu_vc8000e: power-domain@22 {
 						reg = <IMX8MP_POWER_DOMAIN_VPU_VC8000E>;
 						clocks = <&clk IMX8MP_CLK_VPU_VC8KE_ROOT>;
 					};
+
+					pgc_mlmix: power-domain@24 {
+						#power-domain-cells = <0>;
+						reg = <IMX8MP_POWER_DOMAIN_MLMIX>;
+						clocks = <&clk IMX8MP_CLK_ML_AXI>,
+							 <&clk IMX8MP_CLK_ML_AHB>,
+							 <&clk IMX8MP_CLK_NPU_ROOT>;
+					};
 				};
 			};
 		};