diff mbox series

[4/5] cxl/pci: Enable RCD dport AER reporting

Message ID 20221021185615.605233-5-terry.bowman@amd.com
State New
Headers
Series cxl: Log downport PCIe AER and CXL RAS error information |

Commit Message

Terry Bowman Oct. 21, 2022, 6:56 p.m. UTC 
  The RCD downport/upport include 'PCI express' capability with AER
registers. The PCI subsystem is not aware of RCD downport/upport AER
because the downport/upport are not enumerable devices. Since the
downport/upport are not enumerable the existing PCIe AER logic to enable
AER reporting does not apply.

Add logic to the CXL driver to enable AER reporting in the RCRB 'PCI
express' capability. These must be set for correctly reporting the PCIe
AER errors to the RCEC or root port.

Signed-off-by: Terry Bowman <terry.bowman@amd.com>
---
 drivers/cxl/pci.c | 13 +++++++++++++
 1 file changed, 13 insertions(+)
diff mbox series

Patch

diff --git a/drivers/cxl/pci.c b/drivers/cxl/pci.c
index 7f717fb47a36..80a01b304efe 100644
--- a/drivers/cxl/pci.c
+++ b/drivers/cxl/pci.c
@@ -553,6 +553,17 @@  static resource_size_t cxl_get_dport_cap(struct cxl_memdev *cxlmd, int cap_id)
 	return rcrb + offset;
 }
 
+static void cxl_enable_dport_aer(struct cxl_memdev *cxlmd)
+{
+	struct cxl_register_map *map = &cxlmd->cxlds->aer_map;
+	u32 devctl_cap;
+
+	devctl_cap = readl(map->base + PCI_EXP_DEVCTL);
+	devctl_cap |= (PCI_EXP_DEVCTL_CERE | PCI_EXP_DEVCTL_NFERE |
+		       PCI_EXP_DEVCTL_FERE | PCI_EXP_DEVCTL_URRE);
+	writel(devctl_cap, map->base + PCI_EXP_DEVCTL);
+}
+
 static int cxl_setup_dport_aer(struct cxl_memdev *cxlmd, resource_size_t cap_base)
 {
 	struct cxl_register_map *map = &cxlmd->cxlds->aer_map;
@@ -566,6 +577,8 @@  static int cxl_setup_dport_aer(struct cxl_memdev *cxlmd, resource_size_t cap_bas
 	if (!map->base)
 		return -ENOMEM;
 
+	cxl_enable_dport_aer(cxlmd);
+
 	return 0;
 }