Message ID | 20221020111925.30002-2-tinghan.shen@mediatek.com |
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State | New |
Headers |
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[2620:137:e000::1:20]) by mx.google.com with ESMTP id qn24-20020a170907211800b0078d3ba4d567si14462579ejb.422.2022.10.20.04.22.18; Thu, 20 Oct 2022 04:22:55 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@mediatek.com header.s=dk header.b=eFUm1n32; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=mediatek.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230516AbiJTLTr (ORCPT <rfc822;ruipengqi7@gmail.com> + 99 others); Thu, 20 Oct 2022 07:19:47 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51676 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229868AbiJTLTo (ORCPT <rfc822;linux-kernel@vger.kernel.org>); Thu, 20 Oct 2022 07:19:44 -0400 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D6D5D17055; Thu, 20 Oct 2022 04:19:36 -0700 (PDT) X-UUID: 1809ec0bc4104ccebfb3e2ab4eee0f08-20221020 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=5evy1vxNCjxdkl74PuIn+c5ti6HjltIHHQ78bDlgo4o=; b=eFUm1n32WywqOYeuz7F6GEnoYyZLWl7H4lXp4U0lxaH7QECN3xvlFbe2e4xr/oMWfMz7Y+LKjQsRe+4urhL7R9MOnraDJKIyoPgyoCyi23a1PwhVHi9Hzu9AFZAcvznFlpZg1JnCoF1V4q6dwDuPIgI8pKpYCLfIYdXXzzz58K8=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.12,REQID:0f135c70-fa64-4fdc-805f-a351fdd740e6,IP:0,U RL:0,TC:0,Content:-5,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION :release,TS:-5 X-CID-META: VersionHash:62cd327,CLOUDID:12e46ca4-ebb2-41a8-a87c-97702aaf2e20,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:-3,IP:nil,U RL:11|1,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0 X-UUID: 1809ec0bc4104ccebfb3e2ab4eee0f08-20221020 Received: from mtkmbs11n2.mediatek.inc [(172.21.101.187)] by mailgw02.mediatek.com (envelope-from <tinghan.shen@mediatek.com>) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1606574240; Thu, 20 Oct 2022 19:19:28 +0800 Received: from mtkmbs11n2.mediatek.inc (172.21.101.187) by mtkmbs10n2.mediatek.inc (172.21.101.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.3; Thu, 20 Oct 2022 19:19:26 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.15 via Frontend Transport; Thu, 20 Oct 2022 19:19:26 +0800 From: Tinghan Shen <tinghan.shen@mediatek.com> To: Ryder Lee <ryder.lee@mediatek.com>, Jianjun Wang <jianjun.wang@mediatek.com>, Bjorn Helgaas <bhelgaas@google.com>, Rob Herring <robh+dt@kernel.org>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>, Matthias Brugger <matthias.bgg@gmail.com> CC: <linux-pci@vger.kernel.org>, <linux-mediatek@lists.infradead.org>, <devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>, <linux-arm-kernel@lists.infradead.org>, <Project_Global_Chrome_Upstream_Group@mediatek.com>, TingHan Shen <tinghan.shen@mediatek.com> Subject: [PATCH v2 1/3] dt-bindings: PCI: mediatek-gen3: Support mt8195 Date: Thu, 20 Oct 2022 19:19:23 +0800 Message-ID: <20221020111925.30002-2-tinghan.shen@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20221020111925.30002-1-tinghan.shen@mediatek.com> References: <20221020111925.30002-1-tinghan.shen@mediatek.com> MIME-Version: 1.0 Content-Type: text/plain X-MTK: N X-Spam-Status: No, score=-1.7 required=5.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_PASS,UNPARSEABLE_RELAY, URIBL_BLOCKED autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: <linux-kernel.vger.kernel.org> X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1747205463503082301?= X-GMAIL-MSGID: =?utf-8?q?1747205463503082301?= |
Series |
Add driver nodes for MT8195 SoC
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Commit Message
Tinghan Shen
Oct. 20, 2022, 11:19 a.m. UTC
From: Jianjun Wang <jianjun.wang@mediatek.com> In order to support mt8195 pcie node, update the yaml to support new properties of iommu and power-domain, and update the reset-names property to allow only one 'mac' name. Signed-off-by: Jianjun Wang <jianjun.wang@mediatek.com> Signed-off-by: TingHan Shen <tinghan.shen@mediatek.com> --- .../bindings/pci/mediatek-pcie-gen3.yaml | 16 +++++++++++++--- 1 file changed, 13 insertions(+), 3 deletions(-)
Comments
On Thu, Oct 20, 2022 at 07:19:23PM +0800, Tinghan Shen wrote: > From: Jianjun Wang <jianjun.wang@mediatek.com> > > In order to support mt8195 pcie node, update the yaml to support new > properties of iommu and power-domain, and update the reset-names > property to allow only one 'mac' name. > > Signed-off-by: Jianjun Wang <jianjun.wang@mediatek.com> > Signed-off-by: TingHan Shen <tinghan.shen@mediatek.com> > --- > .../bindings/pci/mediatek-pcie-gen3.yaml | 16 +++++++++++++--- > 1 file changed, 13 insertions(+), 3 deletions(-) > > diff --git a/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml b/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml > index c00be39af64e..af271018b134 100644 > --- a/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml > +++ b/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml > @@ -70,14 +70,21 @@ properties: > minItems: 1 > maxItems: 8 > > + iommu-map: > + maxItems: 1 > + > + iommu-map-mask: > + maxItems: 1 This is not a array. It needs a value. Must be 0 if iommu-map only has 1 entry? Or you only support 1 downstream device? > + > resets: > minItems: 1 > maxItems: 2 > > reset-names: > - minItems: 1 > - items: > - - const: phy > + oneOf: > + - items: > + - const: phy > + - const: mac > - const: mac > > clocks: > @@ -107,6 +114,9 @@ properties: > items: > - const: pcie-phy > > + power-domains: > + maxItems: 1 > + > '#interrupt-cells': > const: 1 > > -- > 2.18.0 > >
Hi Rob, Thanks for your review. On Thu, 2022-10-20 at 21:26 -0500, Rob Herring wrote: > On Thu, Oct 20, 2022 at 07:19:23PM +0800, Tinghan Shen wrote: > > From: Jianjun Wang <jianjun.wang@mediatek.com> > > > > In order to support mt8195 pcie node, update the yaml to support > > new > > properties of iommu and power-domain, and update the reset-names > > property to allow only one 'mac' name. > > > > Signed-off-by: Jianjun Wang <jianjun.wang@mediatek.com> > > Signed-off-by: TingHan Shen <tinghan.shen@mediatek.com> > > --- > > .../bindings/pci/mediatek-pcie-gen3.yaml | 16 > > +++++++++++++--- > > 1 file changed, 13 insertions(+), 3 deletions(-) > > > > diff --git a/Documentation/devicetree/bindings/pci/mediatek-pcie- > > gen3.yaml b/Documentation/devicetree/bindings/pci/mediatek-pcie- > > gen3.yaml > > index c00be39af64e..af271018b134 100644 > > --- a/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml > > +++ b/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml > > @@ -70,14 +70,21 @@ properties: > > minItems: 1 > > maxItems: 8 > > > > + iommu-map: > > + maxItems: 1 > > + > > + iommu-map-mask: > > + maxItems: 1 > > This is not a array. It needs a value. Must be 0 if iommu-map only > has 1 > entry? Or you only support 1 downstream device? We only has 1 entry for iommu-map, we'll change it to 0 in the next version. Thanks. > > > + > > resets: > > minItems: 1 > > maxItems: 2 > > > > reset-names: > > - minItems: 1 > > - items: > > - - const: phy > > + oneOf: > > + - items: > > + - const: phy > > + - const: mac > > - const: mac > > > > clocks: > > @@ -107,6 +114,9 @@ properties: > > items: > > - const: pcie-phy > > > > + power-domains: > > + maxItems: 1 > > + > > '#interrupt-cells': > > const: 1 > > > > -- > > 2.18.0 > > > >
diff --git a/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml b/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml index c00be39af64e..af271018b134 100644 --- a/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml +++ b/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml @@ -70,14 +70,21 @@ properties: minItems: 1 maxItems: 8 + iommu-map: + maxItems: 1 + + iommu-map-mask: + maxItems: 1 + resets: minItems: 1 maxItems: 2 reset-names: - minItems: 1 - items: - - const: phy + oneOf: + - items: + - const: phy + - const: mac - const: mac clocks: @@ -107,6 +114,9 @@ properties: items: - const: pcie-phy + power-domains: + maxItems: 1 + '#interrupt-cells': const: 1