Message ID | 20221020095934.1659449-5-peng.fan@oss.nxp.com |
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arm64: dts: imx8m-evk: misc dts update
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Commit Message
Peng Fan (OSS)
Oct. 20, 2022, 9:59 a.m. UTC
From: Clark Wang <xiaoning.wang@nxp.com> Enable pwm1/2/4 support. Enable pwm1 on pin GPIO1_IO01 for DSI_BL_PWM pwm2 on pin GPIO1_IO11 for LVDS_BL_PWM pwm4 on pin SAI5_RXFS for J21-32 Acked-by: Fugang Duan <fugang.duan@nxp.com> Signed-off-by: Clark Wang <xiaoning.wang@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com> --- arch/arm64/boot/dts/freescale/imx8mp-evk.dts | 36 ++++++++++++++++++++ 1 file changed, 36 insertions(+)
Comments
Hi Peng, On 22-10-20, Peng Fan (OSS) wrote: > From: Clark Wang <xiaoning.wang@nxp.com> ... > &iomuxc { > + pinctrl_pwm1: pwm1grp { > + fsl,pins = < > + MX8MP_IOMUXC_GPIO1_IO01__PWM1_OUT 0x116 > + >; > + }; > + > + pinctrl_pwm2: pwm2grp { > + fsl,pins = < > + MX8MP_IOMUXC_GPIO1_IO11__PWM2_OUT 0x116 > + >; > + }; > + > + pinctrl_pwm4: pwm4grp { > + fsl,pins = < > + MX8MP_IOMUXC_SAI5_RXFS__PWM4_OUT 0x116 > + >; > + }; Please sort them alphabetical into the iomuxc node and do not break that sort. Regards, Marco
diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts index a4cddc5a8620..2e29bb3c041c 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts @@ -101,6 +101,24 @@ &A53_3 { cpu-supply = <®_arm>; }; +&pwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm1>; + status = "okay"; +}; + +&pwm2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm2>; + status = "okay"; +}; + +&pwm4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm4>; + status = "okay"; +}; + &eqos { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_eqos>; @@ -465,6 +483,24 @@ &wdog1 { }; &iomuxc { + pinctrl_pwm1: pwm1grp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO01__PWM1_OUT 0x116 + >; + }; + + pinctrl_pwm2: pwm2grp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO11__PWM2_OUT 0x116 + >; + }; + + pinctrl_pwm4: pwm4grp { + fsl,pins = < + MX8MP_IOMUXC_SAI5_RXFS__PWM4_OUT 0x116 + >; + }; + pinctrl_eqos: eqosgrp { fsl,pins = < MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x2