diff mbox series

[PATCHv5,4/6] mmc: dw_mmc-pltfm: socfpga: add method to configure clk-phase

Message ID 20221019170657.68014-5-dinguyen@kernel.org
State New
Headers
Series arm: socfpga: use clk-phase-sd-hs |

Commit Message

Dinh Nguyen Oct. 19, 2022, 5:06 p.m. UTC 
  The clock-phase settings for the SDMMC controller in the SoCFPGA
platforms reside in a register in the System Manager. Add a method
to access that register through the syscon interface.

Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
---
v5: change error handling from of_property_read_variable_u32_array()
    support arm32 by reading the reg_shift
v4: no change
v3: add space before &socfpga_drv_data
v2: simplify clk-phase calculations
---
 drivers/mmc/host/dw_mmc-pltfm.c | 43 ++++++++++++++++++++++++++++++++-
 1 file changed, 42 insertions(+), 1 deletion(-)

Comments

Krzysztof Kozlowski Oct. 21, 2022, 1:32 p.m. UTC | #1 
On 19/10/2022 13:06, Dinh Nguyen wrote:
> The clock-phase settings for the SDMMC controller in the SoCFPGA
> platforms reside in a register in the System Manager. Add a method
> to access that register through the syscon interface.
> 
> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
> ---
> v5: change error handling from of_property_read_variable_u32_array()
>     support arm32 by reading the reg_shift
> v4: no change
> v3: add space before &socfpga_drv_data
> v2: simplify clk-phase calculations
> ---
>  drivers/mmc/host/dw_mmc-pltfm.c | 43 ++++++++++++++++++++++++++++++++-
>  1 file changed, 42 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/mmc/host/dw_mmc-pltfm.c b/drivers/mmc/host/dw_mmc-pltfm.c
> index 9901208be797..74421d13f466 100644
> --- a/drivers/mmc/host/dw_mmc-pltfm.c
> +++ b/drivers/mmc/host/dw_mmc-pltfm.c
> @@ -17,10 +17,16 @@
>  #include <linux/mmc/host.h>
>  #include <linux/mmc/mmc.h>
>  #include <linux/of.h>
> +#include <linux/mfd/altera-sysmgr.h>
> +#include <linux/regmap.h>
>  
>  #include "dw_mmc.h"
>  #include "dw_mmc-pltfm.h"
>  
> +#define SOCFPGA_DW_MMC_CLK_PHASE_STEP	45
> +#define SYSMGR_SDMMC_CTRL_SET(smplsel, drvsel, reg_shift) \
> +	((((smplsel) & 0x7) << reg_shift) | (((drvsel) & 0x7) << 0))
> +
>  int dw_mci_pltfm_register(struct platform_device *pdev,
>  			  const struct dw_mci_drv_data *drv_data)
>  {
> @@ -62,9 +68,44 @@ const struct dev_pm_ops dw_mci_pltfm_pmops = {
>  };
>  EXPORT_SYMBOL_GPL(dw_mci_pltfm_pmops);
>  
> +static int dw_mci_socfpga_priv_init(struct dw_mci *host)
> +{
> +	struct device_node *np = host->dev->of_node;
> +	struct regmap *sys_mgr_base_addr;
> +	u32 clk_phase[2] = {0}, reg_offset, reg_shift;
> +	int i, rc, hs_timing;
> +
> +	rc = of_property_read_variable_u32_array(np, "clk-phase-sd-hs", &clk_phase[0], 2, 0);
> +	if (rc < 0) {
> +		dev_err(host->dev, "clk-phase-sd-hs not found!\n");
> +		return rc;
> +	}
> +
> +	sys_mgr_base_addr = altr_sysmgr_regmap_lookup_by_phandle(np, "altr,sysmgr-syscon");
> +	if (IS_ERR(sys_mgr_base_addr)) {
> +		dev_err(host->dev, "failed to find altr,sys-mgr regmap!\n");
> +		return -ENODEV;

Isn't this now an ABI break? I have an impression we talked about this...

Best regards,
Krzysztof
Dinh Nguyen Oct. 21, 2022, 3:17 p.m. UTC | #2 
On 10/21/22 08:32, Krzysztof Kozlowski wrote:
> On 19/10/2022 13:06, Dinh Nguyen wrote:
>> The clock-phase settings for the SDMMC controller in the SoCFPGA
>> platforms reside in a register in the System Manager. Add a method
>> to access that register through the syscon interface.
>>
>> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
>> ---
>> v5: change error handling from of_property_read_variable_u32_array()
>>      support arm32 by reading the reg_shift
>> v4: no change
>> v3: add space before &socfpga_drv_data
>> v2: simplify clk-phase calculations
>> ---
>>   drivers/mmc/host/dw_mmc-pltfm.c | 43 ++++++++++++++++++++++++++++++++-
>>   1 file changed, 42 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/mmc/host/dw_mmc-pltfm.c b/drivers/mmc/host/dw_mmc-pltfm.c
>> index 9901208be797..74421d13f466 100644
>> --- a/drivers/mmc/host/dw_mmc-pltfm.c
>> +++ b/drivers/mmc/host/dw_mmc-pltfm.c
>> @@ -17,10 +17,16 @@
>>   #include <linux/mmc/host.h>
>>   #include <linux/mmc/mmc.h>
>>   #include <linux/of.h>
>> +#include <linux/mfd/altera-sysmgr.h>
>> +#include <linux/regmap.h>
>>   
>>   #include "dw_mmc.h"
>>   #include "dw_mmc-pltfm.h"
>>   
>> +#define SOCFPGA_DW_MMC_CLK_PHASE_STEP	45
>> +#define SYSMGR_SDMMC_CTRL_SET(smplsel, drvsel, reg_shift) \
>> +	((((smplsel) & 0x7) << reg_shift) | (((drvsel) & 0x7) << 0))
>> +
>>   int dw_mci_pltfm_register(struct platform_device *pdev,
>>   			  const struct dw_mci_drv_data *drv_data)
>>   {
>> @@ -62,9 +68,44 @@ const struct dev_pm_ops dw_mci_pltfm_pmops = {
>>   };
>>   EXPORT_SYMBOL_GPL(dw_mci_pltfm_pmops);
>>   
>> +static int dw_mci_socfpga_priv_init(struct dw_mci *host)
>> +{
>> +	struct device_node *np = host->dev->of_node;
>> +	struct regmap *sys_mgr_base_addr;
>> +	u32 clk_phase[2] = {0}, reg_offset, reg_shift;
>> +	int i, rc, hs_timing;
>> +
>> +	rc = of_property_read_variable_u32_array(np, "clk-phase-sd-hs", &clk_phase[0], 2, 0);
>> +	if (rc < 0) {
>> +		dev_err(host->dev, "clk-phase-sd-hs not found!\n");
>> +		return rc;
>> +	}
>> +
>> +	sys_mgr_base_addr = altr_sysmgr_regmap_lookup_by_phandle(np, "altr,sysmgr-syscon");
>> +	if (IS_ERR(sys_mgr_base_addr)) {
>> +		dev_err(host->dev, "failed to find altr,sys-mgr regmap!\n");
>> +		return -ENODEV;
> 
> Isn't this now an ABI break? I have an impression we talked about this...
> 

My fault, I'll make this optional.

Dinh
diff mbox series

Patch

diff --git a/drivers/mmc/host/dw_mmc-pltfm.c b/drivers/mmc/host/dw_mmc-pltfm.c
index 9901208be797..74421d13f466 100644
--- a/drivers/mmc/host/dw_mmc-pltfm.c
+++ b/drivers/mmc/host/dw_mmc-pltfm.c
@@ -17,10 +17,16 @@ 
 #include <linux/mmc/host.h>
 #include <linux/mmc/mmc.h>
 #include <linux/of.h>
+#include <linux/mfd/altera-sysmgr.h>
+#include <linux/regmap.h>
 
 #include "dw_mmc.h"
 #include "dw_mmc-pltfm.h"
 
+#define SOCFPGA_DW_MMC_CLK_PHASE_STEP	45
+#define SYSMGR_SDMMC_CTRL_SET(smplsel, drvsel, reg_shift) \
+	((((smplsel) & 0x7) << reg_shift) | (((drvsel) & 0x7) << 0))
+
 int dw_mci_pltfm_register(struct platform_device *pdev,
 			  const struct dw_mci_drv_data *drv_data)
 {
@@ -62,9 +68,44 @@  const struct dev_pm_ops dw_mci_pltfm_pmops = {
 };
 EXPORT_SYMBOL_GPL(dw_mci_pltfm_pmops);
 
+static int dw_mci_socfpga_priv_init(struct dw_mci *host)
+{
+	struct device_node *np = host->dev->of_node;
+	struct regmap *sys_mgr_base_addr;
+	u32 clk_phase[2] = {0}, reg_offset, reg_shift;
+	int i, rc, hs_timing;
+
+	rc = of_property_read_variable_u32_array(np, "clk-phase-sd-hs", &clk_phase[0], 2, 0);
+	if (rc < 0) {
+		dev_err(host->dev, "clk-phase-sd-hs not found!\n");
+		return rc;
+	}
+
+	sys_mgr_base_addr = altr_sysmgr_regmap_lookup_by_phandle(np, "altr,sysmgr-syscon");
+	if (IS_ERR(sys_mgr_base_addr)) {
+		dev_err(host->dev, "failed to find altr,sys-mgr regmap!\n");
+		return -ENODEV;
+	}
+
+	of_property_read_u32_index(np, "altr,sysmgr-syscon", 1, &reg_offset);
+	of_property_read_u32_index(np, "altr,sysmgr-syscon", 2, &reg_shift);
+
+	for (i = 0; i < ARRAY_SIZE(clk_phase); i++)
+		clk_phase[i] /= SOCFPGA_DW_MMC_CLK_PHASE_STEP;
+
+	hs_timing = SYSMGR_SDMMC_CTRL_SET(clk_phase[0], clk_phase[1], reg_shift);
+	regmap_write(sys_mgr_base_addr, reg_offset, hs_timing);
+
+	return 0;
+}
+
+static const struct dw_mci_drv_data socfpga_drv_data = {
+	.init		= dw_mci_socfpga_priv_init,
+};
+
 static const struct of_device_id dw_mci_pltfm_match[] = {
 	{ .compatible = "snps,dw-mshc", },
-	{ .compatible = "altr,socfpga-dw-mshc", },
+	{ .compatible = "altr,socfpga-dw-mshc", .data = &socfpga_drv_data, },
 	{ .compatible = "img,pistachio-dw-mshc", },
 	{},
 };