[PATCHv5,3/6] arm: dts: socfpga: Add clk-phase-sd-hs property to the sdmmc node
Commit Message
The sdmmc controller's CIU(Card Interface Unit) clock's phase can be
adjusted through the register in the system manager. Add the binding
"altr,sysmgr-syscon" to the SDMMC node for the driver to access the
system manager. Add the "clk-phase-sd-hs" property in the SDMMC node to
designate the smpsel and drvsel properties for the CIU clock.
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
---
v5: new
---
arch/arm/boot/dts/socfpga.dtsi | 1 +
arch/arm/boot/dts/socfpga_arria10.dtsi | 1 +
arch/arm/boot/dts/socfpga_arria10_mercury_aa1.dtsi | 1 +
arch/arm/boot/dts/socfpga_arria10_socdk_sdmmc.dts | 1 +
arch/arm/boot/dts/socfpga_arria5.dtsi | 1 +
arch/arm/boot/dts/socfpga_cyclone5.dtsi | 1 +
arch/arm/boot/dts/socfpga_cyclone5_mcv.dtsi | 1 +
7 files changed, 7 insertions(+)
@@ -765,6 +765,7 @@ mmc: dwmmc0@ff704000 {
clocks = <&l4_mp_clk>, <&sdmmc_clk_divided>;
clock-names = "biu", "ciu";
resets = <&rst SDMMC_RESET>;
+ altr,sysmgr-syscon = <&sysmgr 0x108 3>;
status = "disabled";
};
@@ -666,6 +666,7 @@ mmc: dwmmc0@ff808000 {
clocks = <&l4_mp_clk>, <&sdmmc_clk>;
clock-names = "biu", "ciu";
resets = <&rst SDMMC_RESET>;
+ altr,sysmgr-syscon = <&sysmgr 0x28 4>;
status = "disabled";
};
@@ -73,6 +73,7 @@ &mmc {
cap-sd-highspeed;
broken-cd;
bus-width = <4>;
+ clk-phase-sd-hs = <0>, <135>;
};
&osc1 {
@@ -12,6 +12,7 @@ &mmc {
cap-mmc-highspeed;
broken-cd;
bus-width = <4>;
+ clk-phase-sd-hs = <0>, <135>;
};
&eccmgr {
@@ -23,6 +23,7 @@ mmc0: dwmmc0@ff704000 {
bus-width = <4>;
cap-mmc-highspeed;
cap-sd-highspeed;
+ clk-phase-sd-hs = <0>, <135>;
};
sysmgr@ffd08000 {
@@ -23,6 +23,7 @@ mmc0: dwmmc0@ff704000 {
bus-width = <4>;
cap-mmc-highspeed;
cap-sd-highspeed;
+ clk-phase-sd-hs = <0>, <135>;
};
sysmgr@ffd08000 {
@@ -18,5 +18,6 @@ memory@0 {
&mmc0 { /* On-SoM eMMC */
bus-width = <8>;
+ clk-phase-sd-hs = <0>, <135>;
status = "okay";
};