| Message ID | 20221018211533.21335-7-afd@ti.com |
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From: Andrew Davis <afd@ti.com>
To: Nishanth Menon <nm@ti.com>, Vignesh Raghavendra <vigneshr@ti.com>,
Tero Kristo <kristo@kernel.org>,
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CC: Andrew Davis <afd@ti.com>
Subject: [PATCH 06/10] arm64: dts: ti: k3-am62: MDIO pinmux should belong to
the MDIO node
Date: Tue, 18 Oct 2022 16:15:29 -0500
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|
| Series |
AM62x Disable Incomplete DT Nodes
|
|
Commit Message
Andrew Davis
Oct. 18, 2022, 9:15 p.m. UTC
Although usually integrated as a child of an Ethernet controller, MDIO
IP has an independent pinout. This pinout should be controlled by
the MDIO node (so if it was to be disabled for instance, the pinmux
state would reflect that).
Move the MDIO pins pinmux to the MIDO nodes.
Signed-off-by: Andrew Davis <afd@ti.com>
---
arch/arm64/boot/dts/ti/k3-am625-sk.dts | 6 ++++--
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/ti/k3-am625-sk.dts b/arch/arm64/boot/dts/ti/k3-am625-sk.dts index 197d329a6082..318ec805ff54 100644 --- a/arch/arm64/boot/dts/ti/k3-am625-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am625-sk.dts @@ -353,8 +353,7 @@ &sdhci1 { &cpsw3g { pinctrl-names = "default"; - pinctrl-0 = <&main_mdio1_pins_default - &main_rgmii1_pins_default + pinctrl-0 = <&main_rgmii1_pins_default &main_rgmii2_pins_default>; }; @@ -369,6 +368,9 @@ &cpsw_port2 { }; &cpsw3g_mdio { + pinctrl-names = "default"; + pinctrl-0 = <&main_mdio1_pins_default>; + cpsw3g_phy0: ethernet-phy@0 { reg = <0>; ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;