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Mon, 17 Oct 2022 20:21:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=stgolabs.net; s=dreamhost; t=1666063282; bh=+F77OywPESqqbC+/oPvGc0AQuP7cONHmICZM40h0KBY=; h=From:To:Cc:Subject:Date:Content-Transfer-Encoding; b=AU8abd9B2gT8pXCbb1HVa2wtEwJD7UPCT98DA++jcGBufcCBd3vRzosXU5rhtQPkZ ANNbuIDk82wJiei8hR++2OkTJaRk3bbr865B8SqGeL4cey05gK0f7zSkSOgi2UggS9 DJu7I8rFna9uAh5I/Nbp6VQzlVn2uP1aw1+e8tThOqOUyRUwEvJg9nfohu2UAavXhL oH3ybDdo4PwtW9icrLt/av6h09Kj78bvAzRFRxgQQxyTaUtbT+KkqFjEfC/QAjZHYE Iy5Q6jYp4IJvE0iHnfeQlX6YYEK8vMFm/MjX+7HWUw/D91iyQw2RWtc4MQowF6IkNU XxHvVCQ2QTRVg== From: Davidlohr Bueso To: dan.j.williams@intel.com Cc: ira.weiny@intel.com, Jonathan.Cameron@huawei.com, dave.jiang@intel.com, alison.schofield@intel.com, bwidawsk@kernel.org, vishal.l.verma@intel.com, a.manzanares@samsung.com, linux-cxl@vger.kernel.org, linux-kernel@vger.kernel.org, dave@stgolabs.net Subject: [PATCH 2/2] cxl/mbox: Wire up irq support Date: Mon, 17 Oct 2022 20:00:10 -0700 Message-Id: <20221018030010.20913-3-dave@stgolabs.net> X-Mailer: git-send-email 2.38.0 In-Reply-To: <20221018030010.20913-1-dave@stgolabs.net> References: <20221018030010.20913-1-dave@stgolabs.net> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1746995602843328252?= X-GMAIL-MSGID: =?utf-8?q?1746995602843328252?= With enough vectors properly allocated, this adds support for (the primary) mailbox interrupt, which is needed for background completion handling, beyond polling. Signed-off-by: Davidlohr Bueso --- drivers/cxl/cxl.h | 1 + drivers/cxl/pci.c | 29 ++++++++++++++++++++++++++++- 2 files changed, 29 insertions(+), 1 deletion(-) diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h index f680450f0b16..13a9743b0012 100644 --- a/drivers/cxl/cxl.h +++ b/drivers/cxl/cxl.h @@ -135,6 +135,7 @@ static inline int ways_to_cxl(unsigned int ways, u8 *iw) /* CXL 2.0 8.2.8.4 Mailbox Registers */ #define CXLDEV_MBOX_CAPS_OFFSET 0x00 #define CXLDEV_MBOX_CAP_PAYLOAD_SIZE_MASK GENMASK(4, 0) +#define CXLDEV_MBOX_CAP_IRQ_MSGNUM_MASK GENMASK(10, 7) #define CXLDEV_MBOX_CTRL_OFFSET 0x04 #define CXLDEV_MBOX_CTRL_DOORBELL BIT(0) #define CXLDEV_MBOX_CMD_OFFSET 0x08 diff --git a/drivers/cxl/pci.c b/drivers/cxl/pci.c index 9c3e95ebaa26..c3f3ee307d7a 100644 --- a/drivers/cxl/pci.c +++ b/drivers/cxl/pci.c @@ -274,6 +274,32 @@ static int cxl_pci_setup_mailbox(struct cxl_dev_state *cxlds) return 0; } +static int cxl_pci_mbox_get_max_msgnum(struct cxl_dev_state *cxlds) +{ + int cap; + + cap = readl(cxlds->regs.mbox + CXLDEV_MBOX_CAPS_OFFSET); + return FIELD_GET(CXLDEV_MBOX_CAP_IRQ_MSGNUM_MASK, cap); +} + +static irqreturn_t cxl_pci_mbox_irq(int irq, void *id) +{ + /* TODO: handle completion of background commands */ + return IRQ_HANDLED; +} + +static void cxl_pci_mbox_irqsetup(struct cxl_dev_state *cxlds) +{ + struct device *dev = cxlds->dev; + struct pci_dev *pdev = to_pci_dev(dev); + int irq; + + irq = cxl_pci_mbox_get_max_msgnum(cxlds); + if (!pci_request_irq(pdev, irq, cxl_pci_mbox_irq, NULL, + cxlds, "%s-mailbox", dev_name(dev))) + dev_dbg(dev, "Mailbox irq (%d) supported", irq); +} + static int cxl_map_regblock(struct pci_dev *pdev, struct cxl_register_map *map) { void __iomem *addr; @@ -442,7 +468,7 @@ struct cxl_irq_cap { }; static const struct cxl_irq_cap cxl_irq_cap_table[] = { - NULL + { "mailbox", cxl_pci_mbox_get_max_msgnum }, }; static void cxl_pci_free_irq_vectors(void *data) @@ -562,6 +588,7 @@ static int cxl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id) return rc; if (!cxl_pci_alloc_irq_vectors(cxlds)) { + cxl_pci_mbox_irqsetup(cxlds); cxlds->has_irq = true; } else cxlds->has_irq = false;