From patchwork Mon Oct 17 16:42:29 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dario Binacchi X-Patchwork-Id: 3603 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:4ac7:0:0:0:0:0 with SMTP id y7csp1545191wrs; Mon, 17 Oct 2022 09:46:58 -0700 (PDT) X-Google-Smtp-Source: AMsMyM4FxRRvbpDXuD9GfKDk0V1yNMmjgSL8h4EqBFnIr50Ni+akdTklE38hI/+WwRt3JCmB0XJK X-Received: by 2002:a17:907:971e:b0:78d:e7ed:7585 with SMTP id jg30-20020a170907971e00b0078de7ed7585mr9203200ejc.258.1666025218219; Mon, 17 Oct 2022 09:46:58 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1666025218; cv=none; d=google.com; s=arc-20160816; b=kLOGpkh4RxJfihw4lgAW8Yr3GXtij3sg3AtPqG2fAJLvejJO0H5H9dbllLqYfDMS1Y x8QoEJurWo5oTBy1wIQhN7+WEv6KmgB7A3dMquPPf+nAA2xtX96SW5nu6o0v/TgkM7GI /n093Ud/hYVyO4Emms6FqPyZFbnOnhNDudNvT2JTorH+8hO6ZdQPOyaSAKJj7qFE6aVF De3gMriAMHYVPGxcTas8h+ODvxhjBPxhVjuUTbJUswi6DE5T6V5wFwROMwKZx25/kWsO OlYOROq9Yc0w8Njlx1AGqBrgarqX0XWLe7+Dx7D6qCL8EmcxExgDcg9m9YRuIkFpqxyu MPVA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=ytjq+5ZqtJJOKrYEaXmPKz3aw/q9ijl/XXCtqz4EuF4=; b=0Jvx8DUUWX7X8p3kjUCUcIUxusoAQDeAdunS9xSlmhisPH59rs5HKDPtNyxfAPgGnY lAB5bD/TB7/j6l4zTSxLPTd00Ov9wnUXip3BIksqxLVKC0eRub5AwyXlRblhAWyqQ8iB fOp8z9BhzPCby98vbKUIZnWraE23AuY8vfrw6NLV0ZMlwLg8sWSv0gg9QDWibU3Bncqi 1aXIQmVF7397yM3j/Yq87DHjdB6QCWAKxwywwzZ95WL9HvbqqylKvB1wlI0/Hy5TUiul 2WHYKI+oyIvFvyghTWGQp3ATrsHmhaPC6wEzJAiBW42TJtK9w9MPvSlq+Bm4ZhdhxEIU TalA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b="hsuH/17g"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id ce24-20020a170906b25800b0078dd3cf41a1si7717335ejb.158.2022.10.17.09.46.32; Mon, 17 Oct 2022 09:46:58 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b="hsuH/17g"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230118AbiJQQnQ (ORCPT + 99 others); Mon, 17 Oct 2022 12:43:16 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43490 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229742AbiJQQnE (ORCPT ); Mon, 17 Oct 2022 12:43:04 -0400 Received: from mail-ej1-x635.google.com (mail-ej1-x635.google.com [IPv6:2a00:1450:4864:20::635]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 56C556EF11 for ; Mon, 17 Oct 2022 09:43:02 -0700 (PDT) Received: by mail-ej1-x635.google.com with SMTP id y14so26210970ejd.9 for ; Mon, 17 Oct 2022 09:43:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=ytjq+5ZqtJJOKrYEaXmPKz3aw/q9ijl/XXCtqz4EuF4=; b=hsuH/17gxJ+I/Td3j928lw4Co9AAW75W1BPqM9/lOi2b1df25a9DgAXI+1EpTOo6HF 9Qgc4smYiQBisr1ab+k5wMtU9xyDfYN/8oHWlj6PC4DMDDazc+cR5F7e5LtUA9NjzMp6 3bjj8tKqaLja+1T+TDrdZvqJWu5bduEDULVb0= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ytjq+5ZqtJJOKrYEaXmPKz3aw/q9ijl/XXCtqz4EuF4=; b=cWx7U0Kf/sRZM9rr+OWNWbr5O/9ya4ryN1P4iMc3DUshbHsjgN1JqoZF1bPXmg51TR wuHYPdfBWL/scj+HpYV6wsaa2ivkY+BlJ6RAnEa73g5Fj45pWdr6rUO8suidwME/j6z3 dViLc9MWgA+8lkvUpZkdR+JB9AZamCv15FXiGTsK1an4y3FUWekCuIJzErPEbZaU8/IQ h+tr6IdtFzVuYUOnlIj9mmG54H385fn7Zh8JSV0tr4rl6SwJk6OrTSDXXh1qmhf0YvAE DqTezdPvEZdPRNuknxnvMwCbiCNenpB06Dumr48zDRMp5atcgAPBIZSLRMnmpuqrcc2Z TLzw== X-Gm-Message-State: ACrzQf3m+FuF/Ze3gX7O2omwJ4EQI3C/NTVlf37zOvSY95zm+5LxyMq4 llm5eLWltGR/0oSofj7+swanDmh/LHOejw== X-Received: by 2002:a17:907:25c9:b0:77b:a343:bd62 with SMTP id ae9-20020a17090725c900b0077ba343bd62mr9568881ejc.660.1666024981531; Mon, 17 Oct 2022 09:43:01 -0700 (PDT) Received: from dario-ThinkPad-T14s-Gen-2i.homenet.telecomitalia.it (host-95-244-101-110.retail.telecomitalia.it. [95.244.101.110]) by smtp.gmail.com with ESMTPSA id a24-20020a1709063a5800b0078128c89439sm6437388ejf.6.2022.10.17.09.43.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 17 Oct 2022 09:43:01 -0700 (PDT) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: michael@amarulasolutions.com, Vincent Mailhol , Krzysztof Kozlowski , Rob Herring , Marc Kleine-Budde , Amarula patchwork , Alexandre Torgue , Dario Binacchi , Krzysztof Kozlowski , Maxime Coquelin , Rob Herring , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-stm32@st-md-mailman.stormreply.com Subject: [RFC PATCH v5 3/5] ARM: dts: stm32: add CAN support on stm32f429 Date: Mon, 17 Oct 2022 18:42:29 +0200 Message-Id: <20221017164231.4192699-4-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20221017164231.4192699-1-dario.binacchi@amarulasolutions.com> References: <20221017164231.4192699-1-dario.binacchi@amarulasolutions.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1746954059107063669?= X-GMAIL-MSGID: =?utf-8?q?1746954059107063669?= Add support for bxcan (Basic eXtended CAN controller) to STM32F429. The chip contains two CAN peripherals, CAN1 the master and CAN2 the slave, that share some of the required logic like clock and filters. This means that the slave CAN can't be used without the master CAN. Signed-off-by: Dario Binacchi --- (no changes since v4) Changes in v4: - Replace the node can@40006400 (compatible "st,stm32f4-bxcan-core") with the gcan@40006600 node ("sysnode" compatible). The gcan node contains clocks and memory addresses shared by the two can nodes of which it's no longer the parent. - Add to can nodes the "st,gcan" property (global can memory) which references the gcan@40006600 node ("sysnode compatibble). Changes in v3: - Remove 'Dario Binacchi ' SOB. - Add "clocks" to can@0 node. arch/arm/boot/dts/stm32f429.dtsi | 29 +++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/arch/arm/boot/dts/stm32f429.dtsi b/arch/arm/boot/dts/stm32f429.dtsi index c31ceb821231..ce08872109b8 100644 --- a/arch/arm/boot/dts/stm32f429.dtsi +++ b/arch/arm/boot/dts/stm32f429.dtsi @@ -362,6 +362,35 @@ i2c3: i2c@40005c00 { status = "disabled"; }; + gcan: gcan@40006600 { + compatible = "st,stm32f4-gcan", "syscon"; + reg = <0x40006600 0x200>; + clocks = <&rcc 0 STM32F4_APB1_CLOCK(CAN1)>; + }; + + can1: can@40006400 { + compatible = "st,stm32f4-bxcan"; + reg = <0x40006400 0x200>; + interrupts = <19>, <20>, <21>, <22>; + interrupt-names = "tx", "rx0", "rx1", "sce"; + resets = <&rcc STM32F4_APB1_RESET(CAN1)>; + clocks = <&rcc 0 STM32F4_APB1_CLOCK(CAN1)>; + st,can-master; + st,gcan = <&gcan>; + status = "disabled"; + }; + + can2: can@40006800 { + compatible = "st,stm32f4-bxcan"; + reg = <0x40006800 0x200>; + interrupts = <63>, <64>, <65>, <66>; + interrupt-names = "tx", "rx0", "rx1", "sce"; + resets = <&rcc STM32F4_APB1_RESET(CAN2)>; + clocks = <&rcc 0 STM32F4_APB1_CLOCK(CAN2)>; + st,gcan = <&gcan>; + status = "disabled"; + }; + dac: dac@40007400 { compatible = "st,stm32f4-dac-core"; reg = <0x40007400 0x400>;