From patchwork Mon Oct 17 08:31:19 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mihai Sain X-Patchwork-Id: 3275 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:4ac7:0:0:0:0:0 with SMTP id y7csp1334013wrs; Mon, 17 Oct 2022 01:35:01 -0700 (PDT) X-Google-Smtp-Source: AMsMyM5Mlfw/sfVbtaD9K2RKtDlOoZuLTha/BwIfW/Vfeco2c/ExllBtgy7TFgI99HHf0aHntZRg X-Received: by 2002:a17:90a:4311:b0:20b:e232:5920 with SMTP id q17-20020a17090a431100b0020be2325920mr12674515pjg.190.1665995699997; Mon, 17 Oct 2022 01:34:59 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1665995699; cv=none; d=google.com; s=arc-20160816; b=d8r6MMDtIuiHBcqVptqGDyGBPrb/fJXPQXtUqke6XHOuoqrXIsNRlQcZjzrKGIZL4g B3wP9JGOM5265imY0YpOCYuz7r4S0RM8koqpFPHMQmwmhZuGeZuK0aQox4UT7aBJ6vn3 wSY/Gy6a2bL41ujGSxCQKvdAlugcMCK2uQEhA8ti+g2WJQYnnjcVDc4F2gZGBT6J3lAc AZT3jVdGlRc/ZpNm9RYY+BNa4R6whrGM9HswpiKzfOMApoSm6zthpCPOAKKd1GLcNmZf zGjHgPBOa7QmVaxKjAChZe50hIBtMWaQfFYPJG3bGmXMZLjVEEc8irYBmiLlnmgl9CBp iaCg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :message-id:date:subject:cc:to:from:dkim-signature; bh=RfiFDXw+uOcRxIy4CU5iyVSsJgBcdyVADTuZ0Z/J0c4=; b=KHemmo8VrOenOX62/ard93VP7iK17HryRFoty7kSzTcOhe75CPV/dwAlB2oDe/Wez9 yCkIXdRTEz0kJHdmMH+8yIiDs0GfwbEP9YfsWWQm++fUcS+v5QNIXaGerY8/mtuVAB4k SBvyl0t5RnBh/JXG+tsxMzSIjZcSmYkdJWMywSOsBXy9MDB1//Gt5N+piDSS3LyoCG61 GMMflWyrK/zrzSfOWsHg75o3yx7knnoTI3CL5c8222p+xl1S3B7B/07fgKqr8qty2/uj Ivpag8SyuCyTa+/SdE9uqChMiGyRN6PJ/DUtgaKaSBGGYX6BjEHMhA09jisvdJ2ocn+9 k4gw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@microchip.com header.s=mchp header.b=MWcfOR9L; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=microchip.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id j184-20020a638bc1000000b00461d9cce57dsi11580080pge.254.2022.10.17.01.34.41; Mon, 17 Oct 2022 01:34:59 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@microchip.com header.s=mchp header.b=MWcfOR9L; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=microchip.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230175AbiJQIbj (ORCPT + 99 others); Mon, 17 Oct 2022 04:31:39 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35986 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229870AbiJQIbi (ORCPT ); Mon, 17 Oct 2022 04:31:38 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6B29FBC91; Mon, 17 Oct 2022 01:31:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1665995497; x=1697531497; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=6Ba4r7Z2zK0pHmIj2H/qZpv6Aa24ieH3Lrajx9mOXQg=; b=MWcfOR9LEsdng6KDekXyA3YgZC/TMFUGNmTTWMENnVTXT6SJ8olPiOdY Z8uanYyVZxdgMVYNSTf6eKA2qTUWdwmlaVjZ/Fy9aXJPAGsNXb+sQiyqR fsBVIIHSxwiIDuwLS3fY6drAlRDKEf7Pb2dXDRwk1hq4DiJXyfLy2NisR V8NyMWfTzYVMCpxmPMWcEDEm2ux5RND50KoQCZ8rA3NHv0GZ4cAtrwmqw ANduqqT8W8I50gjHnFMZkoOgOxCDawIo3X7FpV1EIa7PFKJK30/VuGt3+ 6fPDy2/ZDuQA+Shsw/blVhrrCGQ7LqPjyLB3pWmgQ1SEVryxFsQBe2TR4 g==; X-IronPort-AV: E=Sophos;i="5.95,191,1661842800"; d="scan'208";a="182474316" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa2.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 17 Oct 2022 01:31:36 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.12; Mon, 17 Oct 2022 01:31:35 -0700 Received: from virtualbox.microchip.com (10.10.115.15) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2507.12 via Frontend Transport; Mon, 17 Oct 2022 01:31:32 -0700 From: Mihai Sain To: , , , , , CC: Mihai Sain Subject: [PATCH] ARM: dts: at91: sama7g5: fix signal name of pin PB2 Date: Mon, 17 Oct 2022 11:31:19 +0300 Message-ID: <20221017083119.1643-1-mihai.sain@microchip.com> X-Mailer: git-send-email 2.38.0 MIME-Version: 1.0 X-Spam-Status: No, score=-4.7 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, SPF_HELO_PASS,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1746923107282814363?= X-GMAIL-MSGID: =?utf-8?q?1746923107282814363?= The signal name of pin PB2 with function F is FLEXCOM11_IO1 as it is defined in the datasheet. Fixes: 7540629e2fc7 ("ARM: dts: at91: add sama7g5 SoC DT and sama7g5-ek") Signed-off-by: Mihai Sain Acked-by: Nicolas Ferre Reviewed-by: Tudor Ambarus --- arch/arm/boot/dts/sama7g5-pinfunc.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/sama7g5-pinfunc.h b/arch/arm/boot/dts/sama7g5-pinfunc.h index 4eb30445d205..6e87f0d4b8fc 100644 --- a/arch/arm/boot/dts/sama7g5-pinfunc.h +++ b/arch/arm/boot/dts/sama7g5-pinfunc.h @@ -261,7 +261,7 @@ #define PIN_PB2__FLEXCOM6_IO0 PINMUX_PIN(PIN_PB2, 2, 1) #define PIN_PB2__ADTRG PINMUX_PIN(PIN_PB2, 3, 1) #define PIN_PB2__A20 PINMUX_PIN(PIN_PB2, 4, 1) -#define PIN_PB2__FLEXCOM11_IO0 PINMUX_PIN(PIN_PB2, 6, 3) +#define PIN_PB2__FLEXCOM11_IO1 PINMUX_PIN(PIN_PB2, 6, 3) #define PIN_PB3 35 #define PIN_PB3__GPIO PINMUX_PIN(PIN_PB3, 0, 0) #define PIN_PB3__RF1 PINMUX_PIN(PIN_PB3, 1, 1)