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[2620:137:e000::1:20]) by mx.google.com with ESMTP id k5-20020a63ba05000000b004403d152465si11545772pgf.12.2022.10.16.23.51.40; Sun, 16 Oct 2022 23:51:52 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@kernel.org header.s=k20201202 header.b=Ci5NuFnY; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229978AbiJQGu7 (ORCPT + 99 others); Mon, 17 Oct 2022 02:50:59 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50808 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229818AbiJQGuo (ORCPT ); Mon, 17 Oct 2022 02:50:44 -0400 Received: from dfw.source.kernel.org (dfw.source.kernel.org [139.178.84.217]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 672E913E20; Sun, 16 Oct 2022 23:50:42 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 00FA660F35; Mon, 17 Oct 2022 06:50:42 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 3481EC43160; Mon, 17 Oct 2022 06:50:41 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1665989441; bh=QjLgv94nVfpXem8gTbxoogi1BgbsQEeoIJ4bpkQNxzE=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Ci5NuFnYyAnC5QsBVMvbjkqXubpEuCGvkT+MEiDhC7hnVb7RzTigXVwC68M1ItjWt 1N3FEtLWpUhlgdnNg5Mfmto9V4iQT+RK3ERI249+olv1SoZoasOrTrznFYtUB7QviF iizirRj+Jzv8i0HJzI72jlJHYg+2d0YlRwOut8phwE4vQRNeINGZq/ogC5Gm5sfKn3 LRi9ZzC+tmNvCzhPbRH8qoBSTMze2lhu0Pg8payeRd7qc9YZqMClD+DBOiPwVEVLvr NvWd7/ehKnjR4hf2eIxOZAIYZhBcHf85WUsZXPYN1Id+T5kBMLVC3ZegALE5mPCOrk UECaNuUqNf5oQ== Received: from johan by xi.lan with local (Exim 4.94.2) (envelope-from ) id 1okJxG-00057l-OV; Mon, 17 Oct 2022 08:50:30 +0200 From: Johan Hovold To: Vinod Koul Cc: Andy Gross , Bjorn Andersson , Konrad Dybcio , Dmitry Baryshkov , linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org, Johan Hovold Subject: [PATCH v3 07/11] phy: qcom-qmp-combo: clean up power-down handling Date: Mon, 17 Oct 2022 08:50:09 +0200 Message-Id: <20221017065013.19647-8-johan+linaro@kernel.org> X-Mailer: git-send-email 2.37.3 In-Reply-To: <20221017065013.19647-1-johan+linaro@kernel.org> References: <20221017065013.19647-1-johan+linaro@kernel.org> MIME-Version: 1.0 X-Spam-Status: No, score=-7.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_HI, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1746916619750981877?= X-GMAIL-MSGID: =?utf-8?q?1746916619750981877?= Always define the POWER_DOWN_CONTROL register instead of falling back to the v2 (and v3) offset during power on and power off. Reviewed-by: Dmitry Baryshkov Signed-off-by: Johan Hovold --- drivers/phy/qualcomm/phy-qcom-qmp-combo.c | 19 +++++-------------- 1 file changed, 5 insertions(+), 14 deletions(-) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-combo.c b/drivers/phy/qualcomm/phy-qcom-qmp-combo.c index c21512b9ab52..7b434e2ee640 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-combo.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-combo.c @@ -121,6 +121,7 @@ static const unsigned int qmp_v3_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = { [QPHY_SW_RESET] = 0x00, [QPHY_START_CTRL] = 0x08, [QPHY_PCS_STATUS] = 0x174, + [QPHY_PCS_POWER_DOWN_CONTROL] = 0x04, [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x0d8, [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x0dc, [QPHY_PCS_LFPS_RXTERM_IRQ_STATUS] = 0x170, @@ -1991,13 +1992,8 @@ static int qmp_combo_com_init(struct qmp_phy *qphy) qphy_clrbits(dp_com, QPHY_V3_DP_COM_SWI_CTRL, 0x03); qphy_clrbits(dp_com, QPHY_V3_DP_COM_SW_RESET, SW_RESET); - if (cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL]) - qphy_setbits(pcs, - cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL], - cfg->pwrdn_ctrl); - else - qphy_setbits(pcs, QPHY_V2_PCS_POWER_DOWN_CONTROL, - cfg->pwrdn_ctrl); + qphy_setbits(pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL], + cfg->pwrdn_ctrl); mutex_unlock(&qmp->phy_mutex); @@ -2144,13 +2140,8 @@ static int qmp_combo_power_off(struct phy *phy) qphy_clrbits(qphy->pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl); /* Put PHY into POWER DOWN state: active low */ - if (cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL]) { - qphy_clrbits(qphy->pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL], - cfg->pwrdn_ctrl); - } else { - qphy_clrbits(qphy->pcs, QPHY_V2_PCS_POWER_DOWN_CONTROL, - cfg->pwrdn_ctrl); - } + qphy_clrbits(qphy->pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL], + cfg->pwrdn_ctrl); } return 0;