Message ID | 20221013183854.21087-4-vidyas@nvidia.com |
---|---|
State | New |
Headers |
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Thu, 13 Oct 2022 11:39:23 -0700 Received: from drhqmail203.nvidia.com (10.126.190.182) by drhqmail202.nvidia.com (10.126.190.181) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.29; Thu, 13 Oct 2022 11:39:23 -0700 Received: from vidyas-desktop.nvidia.com (10.127.8.9) by mail.nvidia.com (10.126.190.182) with Microsoft SMTP Server id 15.2.986.29 via Frontend Transport; Thu, 13 Oct 2022 11:39:18 -0700 From: Vidya Sagar <vidyas@nvidia.com> To: <lpieralisi@kernel.org>, <robh@kernel.org>, <kw@linux.com>, <bhelgaas@google.com>, <thierry.reding@gmail.com>, <jonathanh@nvidia.com>, <kishon@ti.com>, <vkoul@kernel.org>, <mani@kernel.org>, <Sergey.Semin@baikalelectronics.ru>, <ffclaire1224@gmail.com> CC: <linux-pci@vger.kernel.org>, <linux-tegra@vger.kernel.org>, <linux-kernel@vger.kernel.org>, <linux-phy@lists.infradead.org>, <kthota@nvidia.com>, <mmaddireddy@nvidia.com>, <vidyas@nvidia.com>, <sagar.tv@gmail.com> Subject: [PATCH V3 03/21] PCI: tegra194: Fix polling delay for L2 state Date: Fri, 14 Oct 2022 00:08:36 +0530 Message-ID: <20221013183854.21087-4-vidyas@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20221013183854.21087-1-vidyas@nvidia.com> References: <20221013183854.21087-1-vidyas@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 Content-Type: text/plain X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM6NAM11FT074:EE_|PH0PR12MB5605:EE_ X-MS-Office365-Filtering-Correlation-Id: 8f8260e9-1b4f-43d6-cec7-08daad4a45a4 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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Series |
Enhancements to pcie-tegra194 driver
|
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Commit Message
Vidya Sagar
Oct. 13, 2022, 6:38 p.m. UTC
As per PCIe spec r6.0, sec 5.3.3.2.1, after sending PME_Turn_Off message,
Root port should wait for 1~10 msec for PME_TO_Ack message. Currently,
driver is polling for 10 msec with 1 usec delay which is aggressive.
Change it to 10 msec polling with 100 usec delay. Since this function
is used in non-atomic context only, use non-atomic poll function.
Fixes: 56e15a238d92 ("PCI: tegra: Add Tegra194 PCIe support")
Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
---
V3:
* Changed atomic call to non-atomic call
* Reworded the commit message
V2:
* None
drivers/pci/controller/dwc/pcie-tegra194.c | 9 +++++----
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c index a33c86e3de9d..685aee378c93 100644 --- a/drivers/pci/controller/dwc/pcie-tegra194.c +++ b/drivers/pci/controller/dwc/pcie-tegra194.c @@ -207,7 +207,8 @@ #define CAP_SPCIE_CAP_OFF_USP_TX_PRESET0_MASK GENMASK(11, 8) #define CAP_SPCIE_CAP_OFF_USP_TX_PRESET0_SHIFT 8 -#define PME_ACK_TIMEOUT 10000 +#define PME_ACK_DELAY 100 /* 100 us */ +#define PME_ACK_TIMEOUT 10000 /* 10 ms */ #define LTSSM_TIMEOUT 50000 /* 50ms */ @@ -1611,9 +1612,9 @@ static int tegra_pcie_try_link_l2(struct tegra_pcie_dw *pcie) val |= APPL_PM_XMT_TURNOFF_STATE; appl_writel(pcie, val, APPL_RADM_STATUS); - return readl_poll_timeout_atomic(pcie->appl_base + APPL_DEBUG, val, - val & APPL_DEBUG_PM_LINKST_IN_L2_LAT, - 1, PME_ACK_TIMEOUT); + return readl_poll_timeout(pcie->appl_base + APPL_DEBUG, val, + val & APPL_DEBUG_PM_LINKST_IN_L2_LAT, + PME_ACK_DELAY, PME_ACK_TIMEOUT); } static void tegra_pcie_dw_pme_turnoff(struct tegra_pcie_dw *pcie)