diff mbox series

[v4,2/3] iommu/mediatek: add support for 6-bit encoded port IDs

Message ID 20221001-iommu-support-v4-2-f1e13438dfd2@baylibre.com
State New
Headers
Series iommu/mediatek: Add mt8365 iommu support |

Commit Message

Alexandre Mergnat Oct. 14, 2022, 8:45 a.m. UTC 
  From: Fabien Parent <fparent@baylibre.com>

Until now the port ID was always encoded as a 5-bit data. On MT8365,
the port ID is encoded as a 6-bit data. This requires to add extra
macro F_MMU_INT_ID_LARB_ID_EXT, and F_MMU_INT_ID_PORT_ID_EXT in order
to support 6-bit encoded port IDs.

Signed-off-by: Fabien Parent <fparent@baylibre.com>
Signed-off-by: Markus Schneider-Pargmann <msp@baylibre.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Signed-off-by: Alexandre Mergnat <amergnat@baylibre.com>
---
 drivers/iommu/mtk_iommu.c | 17 +++++++++++++++--
 1 file changed, 15 insertions(+), 2 deletions(-)

Comments

Yong Wu Oct. 15, 2022, 3:28 a.m. UTC | #1 
On Fri, 2022-10-14 at 10:45 +0200, Alexandre Mergnat wrote:
> From: Fabien Parent <fparent@baylibre.com>
> 
> Until now the port ID was always encoded as a 5-bit data. On MT8365,
> the port ID is encoded as a 6-bit data. This requires to add extra
> macro F_MMU_INT_ID_LARB_ID_EXT, and F_MMU_INT_ID_PORT_ID_EXT in order
> to support 6-bit encoded port IDs.
> 
> Signed-off-by: Fabien Parent <fparent@baylibre.com>
> Signed-off-by: Markus Schneider-Pargmann <msp@baylibre.com>
> Reviewed-by: AngeloGioacchino Del Regno <
> angelogioacchino.delregno@collabora.com>
> Signed-off-by: Alexandre Mergnat <amergnat@baylibre.com>
> ---
>  drivers/iommu/mtk_iommu.c | 17 +++++++++++++++--
>  1 file changed, 15 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c
> index 5a4e00e4bbbc..50195a900611 100644
> --- a/drivers/iommu/mtk_iommu.c
> +++ b/drivers/iommu/mtk_iommu.c
> @@ -108,8 +108,12 @@
>  #define F_MMU_INT_ID_SUB_COMM_ID(a)		(((a) >> 7) & 0x3)
>  #define F_MMU_INT_ID_COMM_ID_EXT(a)		(((a) >> 10) & 0x7)
>  #define F_MMU_INT_ID_SUB_COMM_ID_EXT(a)		(((a) >> 7) &
> 0x7)
> +/* Macro for 5 bits length port ID field (default) */
>  #define F_MMU_INT_ID_LARB_ID(a)			(((a) >> 7) &
> 0x7)
>  #define F_MMU_INT_ID_PORT_ID(a)			(((a) >> 2) &
> 0x1f)
> +/* Macro for 6 bits length port ID field */
> +#define F_MMU_INT_ID_LARB_ID_EXT(a)		(((a) >> 8) & 0x7)
> +#define F_MMU_INT_ID_PORT_ID_EXT(a)		(((a) >> 2) & 0x3f)

So far only mt8365 use 6 bits here. We could rename more detailly:

like F_MMU_INT_ID_PORT_ID_MT8365 or keep consistent with the below flag
name: F_MMU_INT_ID_PORT_ID_WID_6.

>  
>  #define MTK_PROTECT_PA_ALIGN			256
>  #define MTK_IOMMU_BANK_SZ			0x1000
> @@ -139,6 +143,7 @@
>  #define IFA_IOMMU_PCIE_SUPPORT		BIT(16)
>  #define PGTABLE_PA_35_EN		BIT(17)
>  #define TF_PORT_TO_ADDR_MT8173		BIT(18)
> +#define HAS_INT_ID_PORT_WIDTH_6		BIT(19)

HAS_SUB_COM means the SoC has SMI sub_common. this only indicate
port width is 6bits. No need "HAS_". I think INT_ID_PORT_WIDTH_6 is ok.

>  
>  #define MTK_IOMMU_HAS_FLAG_MASK(pdata, _x, mask)	\
>  				((((pdata)->flags) & (mask)) == (_x))
> @@ -441,7 +446,11 @@ static irqreturn_t mtk_iommu_isr(int irq, void
> *dev_id)
>  	fault_pa |= (u64)pa34_32 << 32;
>  
>  	if (MTK_IOMMU_IS_TYPE(plat_data, MTK_IOMMU_TYPE_MM)) {
> -		fault_port = F_MMU_INT_ID_PORT_ID(regval);
> +		if (MTK_IOMMU_HAS_FLAG(plat_data,
> HAS_INT_ID_PORT_WIDTH_6)) {
> +			fault_port = F_MMU_INT_ID_PORT_ID_EXT(regval);
> +		} else {
> +			fault_port = F_MMU_INT_ID_PORT_ID(regval);
> +		}
>  		if (MTK_IOMMU_HAS_FLAG(plat_data, HAS_SUB_COMM_2BITS))
> {
>  			fault_larb = F_MMU_INT_ID_COMM_ID(regval);
>  			sub_comm = F_MMU_INT_ID_SUB_COMM_ID(regval);
> @@ -449,7 +458,11 @@ static irqreturn_t mtk_iommu_isr(int irq, void
> *dev_id)
>  			fault_larb = F_MMU_INT_ID_COMM_ID_EXT(regval);
>  			sub_comm =
> F_MMU_INT_ID_SUB_COMM_ID_EXT(regval);
>  		} else {
> -			fault_larb = F_MMU_INT_ID_LARB_ID(regval);
> +			if (MTK_IOMMU_HAS_FLAG(plat_data,
> HAS_INT_ID_PORT_WIDTH_6)) {
> +				fault_larb =
> F_MMU_INT_ID_LARB_ID_EXT(regval);
> +			} else {
> +				fault_larb =
> F_MMU_INT_ID_LARB_ID(regval);
> +			}
>  		}

It has two checking about this new flag. How about this?

if (MTK_IOMMU_HAS_FLAG(plat_data, HAS_SUB_COMM_2BITS)) {
    fault_larb
= x
    sub_com = x
    fault_port = F_MMU_INT_ID_PORT_ID(regval); //New add    
} else if (MTK_IOMMU_HAS_FLAG(plat_data, HAS_SUB_COMM_3BITS)) {
    fault_larb = x
    sub_com = x
    fault_port= F_MMU_INT_ID_PORT_ID(regval); //New add 
} else if (MTK_IOMMU_HAS_FLAG(plat_data, HAS_INT_ID_PORT_WIDTH_6)) { /*
mt8365 */
    fault_port = F_MMU_INT_ID_PORT_ID_EXT(regval);
    fault_larb =
F_MMU_INT_ID_LARB_ID_EXT(regval);
} else {
    fault_larb = F_MMU_INT_ID_LARB_ID(regval);
    fault_port = F_MMU_INT_ID_PORT_ID(regval);
}
>  		fault_larb = data->plat_data-
> >larbid_remap[fault_larb][sub_comm];
>  	}
>
diff mbox series

Patch

diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c
index 5a4e00e4bbbc..50195a900611 100644
--- a/drivers/iommu/mtk_iommu.c
+++ b/drivers/iommu/mtk_iommu.c
@@ -108,8 +108,12 @@ 
 #define F_MMU_INT_ID_SUB_COMM_ID(a)		(((a) >> 7) & 0x3)
 #define F_MMU_INT_ID_COMM_ID_EXT(a)		(((a) >> 10) & 0x7)
 #define F_MMU_INT_ID_SUB_COMM_ID_EXT(a)		(((a) >> 7) & 0x7)
+/* Macro for 5 bits length port ID field (default) */
 #define F_MMU_INT_ID_LARB_ID(a)			(((a) >> 7) & 0x7)
 #define F_MMU_INT_ID_PORT_ID(a)			(((a) >> 2) & 0x1f)
+/* Macro for 6 bits length port ID field */
+#define F_MMU_INT_ID_LARB_ID_EXT(a)		(((a) >> 8) & 0x7)
+#define F_MMU_INT_ID_PORT_ID_EXT(a)		(((a) >> 2) & 0x3f)
 
 #define MTK_PROTECT_PA_ALIGN			256
 #define MTK_IOMMU_BANK_SZ			0x1000
@@ -139,6 +143,7 @@ 
 #define IFA_IOMMU_PCIE_SUPPORT		BIT(16)
 #define PGTABLE_PA_35_EN		BIT(17)
 #define TF_PORT_TO_ADDR_MT8173		BIT(18)
+#define HAS_INT_ID_PORT_WIDTH_6		BIT(19)
 
 #define MTK_IOMMU_HAS_FLAG_MASK(pdata, _x, mask)	\
 				((((pdata)->flags) & (mask)) == (_x))
@@ -441,7 +446,11 @@  static irqreturn_t mtk_iommu_isr(int irq, void *dev_id)
 	fault_pa |= (u64)pa34_32 << 32;
 
 	if (MTK_IOMMU_IS_TYPE(plat_data, MTK_IOMMU_TYPE_MM)) {
-		fault_port = F_MMU_INT_ID_PORT_ID(regval);
+		if (MTK_IOMMU_HAS_FLAG(plat_data, HAS_INT_ID_PORT_WIDTH_6)) {
+			fault_port = F_MMU_INT_ID_PORT_ID_EXT(regval);
+		} else {
+			fault_port = F_MMU_INT_ID_PORT_ID(regval);
+		}
 		if (MTK_IOMMU_HAS_FLAG(plat_data, HAS_SUB_COMM_2BITS)) {
 			fault_larb = F_MMU_INT_ID_COMM_ID(regval);
 			sub_comm = F_MMU_INT_ID_SUB_COMM_ID(regval);
@@ -449,7 +458,11 @@  static irqreturn_t mtk_iommu_isr(int irq, void *dev_id)
 			fault_larb = F_MMU_INT_ID_COMM_ID_EXT(regval);
 			sub_comm = F_MMU_INT_ID_SUB_COMM_ID_EXT(regval);
 		} else {
-			fault_larb = F_MMU_INT_ID_LARB_ID(regval);
+			if (MTK_IOMMU_HAS_FLAG(plat_data, HAS_INT_ID_PORT_WIDTH_6)) {
+				fault_larb = F_MMU_INT_ID_LARB_ID_EXT(regval);
+			} else {
+				fault_larb = F_MMU_INT_ID_LARB_ID(regval);
+			}
 		}
 		fault_larb = data->plat_data->larbid_remap[fault_larb][sub_comm];
 	}