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[2a02:8440:6241:7429:3074:96af:9642:4]) by smtp.gmail.com with ESMTPSA id z11-20020a05600c0a0b00b003c6bd91caa5sm2818223wmp.17.2022.10.14.08.20.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 14 Oct 2022 08:20:05 -0700 (PDT) From: Guillaume Ranquet Date: Fri, 14 Oct 2022 17:15:55 +0200 Subject: [PATCH v2 02/12] dt-bindings: display: mediatek: add MT8195 hdmi bindings MIME-Version: 1.0 Message-Id: <20220919-v2-2-8419dcf4f09d@baylibre.com> References: <20220919-v2-0-8419dcf4f09d@baylibre.com> In-Reply-To: <20220919-v2-0-8419dcf4f09d@baylibre.com> To: Chunfeng Yun , David Airlie , Philipp Zabel , Jitao shi , CK Hu , Rob Herring , Krzysztof Kozlowski , Vinod Koul , Kishon Vijay Abraham I , Matthias Brugger , Daniel Vetter , Chun-Kuang Hu Cc: Guillaume Ranquet , stuart.lee@mediatek.com, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, AngeloGioacchino Del Regno , linux-kernel@vger.kernel.org, Krzysztof Kozlowski , mac.shen@mediatek.com, linux-mediatek@lists.infradead.org, dri-devel@lists.freedesktop.org X-Mailer: b4 0.11.0-dev X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1746676885022005907?= X-GMAIL-MSGID: =?utf-8?q?1746676885022005907?= Add mt8195 SoC bindings for hdmi and hdmi-ddc Signed-off-by: Guillaume Ranquet --- .../bindings/display/mediatek/mediatek,hdmi.yaml | 67 +++++++++++++++++----- .../display/mediatek/mediatek,mt8195-hdmi-ddc.yaml | 51 ++++++++++++++++ 2 files changed, 104 insertions(+), 14 deletions(-) diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi.yaml index bdaf0b51e68c..955026cd7ca5 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi.yaml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi.yaml @@ -21,26 +21,21 @@ properties: - mediatek,mt7623-hdmi - mediatek,mt8167-hdmi - mediatek,mt8173-hdmi + - mediatek,mt8195-hdmi reg: maxItems: 1 - interrupts: - maxItems: 1 - clocks: - items: - - description: Pixel Clock - - description: HDMI PLL - - description: Bit Clock - - description: S/PDIF Clock + minItems: 4 + maxItems: 4 clock-names: - items: - - const: pixel - - const: pll - - const: bclk - - const: spdif + minItems: 4 + maxItems: 4 + + interrupts: + maxItems: 1 phys: maxItems: 1 @@ -58,6 +53,9 @@ properties: description: | phandle link and register offset to the system configuration registers. + power-domains: + maxItems: 1 + ports: $ref: /schemas/graph.yaml#/properties/ports @@ -86,9 +84,50 @@ required: - clock-names - phys - phy-names - - mediatek,syscon-hdmi - ports +allOf: + - if: + properties: + compatible: + contains: + const: mediatek,mt8195-hdmi + then: + properties: + clocks: + items: + - description: APB + - description: HDCP + - description: HDCP 24M + - description: Split HDMI + clock-names: + items: + - const: hdmi_apb_sel + - const: hdcp_sel + - const: hdcp24_sel + - const: split_hdmi + + required: + - power-domains + else: + properties: + clocks: + items: + - description: Pixel Clock + - description: HDMI PLL + - description: Bit Clock + - description: S/PDIF Clock + + clock-names: + items: + - const: pixel + - const: pll + - const: bclk + - const: spdif + + required: + - mediatek,syscon-hdmi + additionalProperties: false examples: diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,mt8195-hdmi-ddc.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,mt8195-hdmi-ddc.yaml new file mode 100644 index 000000000000..0fe0a2a2f17f --- /dev/null +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,mt8195-hdmi-ddc.yaml @@ -0,0 +1,51 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/mediatek/mediatek,mt8195-hdmi-ddc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Mediatek HDMI DDC for mt8195 + +maintainers: + - CK Hu + - Jitao shi + +description: | + The HDMI DDC i2c controller is used to interface with the HDMI DDC pins. + +properties: + compatible: + enum: + - mediatek,mt8195-hdmi-ddc + + clocks: + maxItems: 1 + + clock-names: + items: + - const: ddc + + mediatek,hdmi: + $ref: /schemas/types.yaml#/definitions/phandle + description: + A phandle to the mt8195 hdmi controller + +required: + - compatible + - clocks + - clock-names + +additionalProperties: false + +examples: + - | + #include + #include + hdmiddc0: ddc_i2c { + compatible = "mediatek,mt8195-hdmi-ddc"; + mediatek,hdmi = <&hdmi0>; + clocks = <&clk26m>; + clock-names = "ddc"; + }; + +...