Message ID | 1efa9a64499767d939efadd0aef897ac4a6e54eb.1680693149.git.quic_varada@quicinc.com |
---|---|
State | New |
Headers |
Return-Path: <linux-kernel-owner@vger.kernel.org> Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp235634vqo; Wed, 5 Apr 2023 04:46:01 -0700 (PDT) X-Google-Smtp-Source: AKy350a2MIMhgB1y6mWMNPc1H6/waI+9pXrbIF8sBBe9dwOYN7L3I7g2Gn43GKiPVH47gm8VjczZ X-Received: by 2002:aa7:c386:0:b0:4fb:59bb:ce71 with SMTP id k6-20020aa7c386000000b004fb59bbce71mr1565436edq.36.1680695161552; Wed, 05 Apr 2023 04:46:01 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1680695161; cv=none; d=google.com; s=arc-20160816; b=f6pPhfxUE4WG7U2TGq3avWAXgNGE3wykDeZMJOYPfeU0JUOVtelX6yMeJyWJva3Hv9 g0R4jQ91E3ycRIhC9CVeAdyA9Jj9plHOq0Rwr8RPuGolX65/MrQAuQAVhVScmQIcihjm Ypwed/mmRueHn/l+Aj0yYQXgljf6CW/E7/HfPZkzNM1fVUlDEBnAz5a/3UWapMAz8wAi IYpp3zrgeurUDvCxg79NPfpqFc/0dflD7HzYoMN03iWqIU0YEkW/ngNVPl70ITpcoO4Q vuqJ7wnCQO8S9UrHCDAEG/FOpFpGpkabv0l4Akx6e085BWRQOEyuBsmDfvMl9ess0RMe /rcA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=MP8vY5b3c3LbYhyxq8wfVu3i4CjBKlxbpCsn4bvRI78=; b=rluFIpsXVreaCNfmtNVbE3/KY81dq4/f6ZvW10e99JSdWU1jUoDekVxTG1s7kcLi3O wT2i4V4ncAApr84zH9bGbjGJJjKS9dZ8cAHSBgsNBZyJ9ck2OAMrEe5PP3TP25pyrPRd 739aYnDjZ0o1wptsM5E37CdjCHsvJAPxq+Yq0L9apWFlRhr14B6lJlhP03rf74fIXFJ+ YNTMzLh49CZq5ctkWTuNQzv/05OCxHwVsT5RYKBCLN+2kHkL0dK0rXN35fztDTi7R6IZ SuAuhwGjpWJhGdPeluaRNxifsU3mr6Z8VQOh9Xcj7g0iG/76KpoCqPbML/Yw0A3HcGbj 1RYA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b=koBvBqDS; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id i16-20020aa7c9d0000000b004bf976a1b56si2228142edt.627.2023.04.05.04.45.37; Wed, 05 Apr 2023 04:46:01 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b=koBvBqDS; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237932AbjDELmM (ORCPT <rfc822;lkml4gm@gmail.com> + 99 others); Wed, 5 Apr 2023 07:42:12 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51812 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237576AbjDELmE (ORCPT <rfc822;linux-kernel@vger.kernel.org>); Wed, 5 Apr 2023 07:42:04 -0400 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3E9C030FD; Wed, 5 Apr 2023 04:42:03 -0700 (PDT) Received: from pps.filterd (m0279863.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 335ApmmR004370; Wed, 5 Apr 2023 11:41:54 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=qcppdkim1; bh=MP8vY5b3c3LbYhyxq8wfVu3i4CjBKlxbpCsn4bvRI78=; b=koBvBqDS0gRj49Jvog1xBD+qz2n6YwbnPGyVKrKMDcaIZjbrOB6C+r7EFHTY5kOBP7Wq kgXUbI6/3L2xtv+4Xvd9Jr+gyXw4Bier/V8hc0v3cKmQCaG4tnTdkdqaPhCcLSSqvJy2 V9tUMyP4EpOG3DfUWDrle+jre0KfXdrhsMAqipHqc9524npoiju8KhUcFr53RgKrqn2t aqGdTf1wgWrIxkrGvG6gHi+v6frlNnXS27S53kAb0lsqKw8VdJWtehdPXDRU1uvHssx+ /iBwWcJIWYhTHRRTcn107O4HqrflqA2zrodAE6cU4pEitMwFhLQFGYJVv+O7hbTo+UDP dg== Received: from nasanppmta01.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3prpg22ftn-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 05 Apr 2023 11:41:53 +0000 Received: from nasanex01a.na.qualcomm.com (nasanex01a.na.qualcomm.com [10.52.223.231]) by NASANPPMTA01.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 335Bfrsf021910 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 5 Apr 2023 11:41:53 GMT Received: from varda-linux.qualcomm.com (10.80.80.8) by nasanex01a.na.qualcomm.com (10.52.223.231) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.42; Wed, 5 Apr 2023 04:41:47 -0700 From: Varadarajan Narayanan <quic_varada@quicinc.com> To: <agross@kernel.org>, <andersson@kernel.org>, <konrad.dybcio@linaro.org>, <vkoul@kernel.org>, <kishon@kernel.org>, <robh+dt@kernel.org>, <krzysztof.kozlowski+dt@linaro.org>, <gregkh@linuxfoundation.org>, <mturquette@baylibre.com>, <sboyd@kernel.org>, <quic_wcheng@quicinc.com>, <linux-arm-msm@vger.kernel.org>, <linux-phy@lists.infradead.org>, <devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>, <linux-usb@vger.kernel.org>, <linux-clk@vger.kernel.org> CC: Varadarajan Narayanan <quic_varada@quicinc.com> Subject: [PATCH v8 2/8] dt-bindings: phy: qcom,qmp-usb: Add IPQ9574 USB3 PHY Date: Wed, 5 Apr 2023 17:11:21 +0530 Message-ID: <1efa9a64499767d939efadd0aef897ac4a6e54eb.1680693149.git.quic_varada@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <cover.1680693149.git.quic_varada@quicinc.com> References: <cover.1680693149.git.quic_varada@quicinc.com> MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nasanex01a.na.qualcomm.com (10.52.223.231) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: B6iaiRNoKuyA0cIResqyGA-h3aK3622A X-Proofpoint-ORIG-GUID: B6iaiRNoKuyA0cIResqyGA-h3aK3622A X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.942,Hydra:6.0.573,FMLib:17.11.170.22 definitions=2023-04-05_07,2023-04-05_01,2023-02-09_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 adultscore=0 bulkscore=0 impostorscore=0 clxscore=1015 priorityscore=1501 suspectscore=0 mlxscore=0 spamscore=0 mlxlogscore=999 lowpriorityscore=0 malwarescore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2303200000 definitions=main-2304050106 X-Spam-Status: No, score=-0.9 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_LOW,SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: <linux-kernel.vger.kernel.org> X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1762336610035371035?= X-GMAIL-MSGID: =?utf-8?q?1762336610035371035?= |
Series |
Enable IPQ9754 USB
|
|
Commit Message
Varadarajan Narayanan
April 5, 2023, 11:41 a.m. UTC
Add dt-bindings for USB3 PHY found on Qualcomm IPQ9574
Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
---
Changes in v8:
- Update clock names for ipq9574
Changes in v6:
- Made power-domains optional
Note: In the earlier patch sets, had used the (legacy)
specification available in qcom,msm8996-qmp-usb3-phy.yaml. Moved
to newer specification in qcom,sc8280xp-qmp-usb3-uni-phy.yaml
---
.../phy/qcom,sc8280xp-qmp-usb3-uni-phy.yaml | 43 +++++++++++++++++++---
1 file changed, 37 insertions(+), 6 deletions(-)
Comments
On 05/04/2023 13:41, Varadarajan Narayanan wrote: > Add dt-bindings for USB3 PHY found on Qualcomm IPQ9574 > > Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com> > --- > Changes in v8: > - Update clock names for ipq9574 > > Changes in v6: > - Made power-domains optional > > Note: In the earlier patch sets, had used the (legacy) > specification available in qcom,msm8996-qmp-usb3-phy.yaml. Moved > to newer specification in qcom,sc8280xp-qmp-usb3-uni-phy.yaml > --- > .../phy/qcom,sc8280xp-qmp-usb3-uni-phy.yaml | 43 +++++++++++++++++++--- > 1 file changed, 37 insertions(+), 6 deletions(-) > > diff --git a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-usb3-uni-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-usb3-uni-phy.yaml > index 16fce10..e902a0d 100644 > --- a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-usb3-uni-phy.yaml > +++ b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-usb3-uni-phy.yaml > @@ -16,6 +16,7 @@ description: > properties: > compatible: > enum: > + - qcom,ipq9574-qmp-usb3-phy > - qcom,sc8280xp-qmp-usb3-uni-phy > > reg: > @@ -25,11 +26,7 @@ properties: > maxItems: 4 > > clock-names: > - items: > - - const: aux > - - const: ref > - - const: com_aux > - - const: pipe > + maxItems: 4 > > power-domains: > maxItems: 1 > @@ -60,7 +57,6 @@ required: > - reg > - clocks > - clock-names > - - power-domains > - resets > - reset-names > - vdda-phy-supply > @@ -71,6 +67,41 @@ required: > > additionalProperties: false > > +allOf: As you can see in example-schema, allOf goes before additionalProperties: false. > + - if: > + properties: > + compatible: > + contains: > + enum: > + - qcom,ipq9574-qmp-usb3-phy > + then: > + properties: > + clocks: > + maxItems: 4 Don't need clocks here. > + clock-names: > + items: > + - const: aux > + - const: ref > + - const: cfg_ahb > + - const: pipe > + > + - if: > + properties: > + compatible: > + contains: > + enum: > + - qcom,sc8280xp-qmp-usb3-uni-phy > + then: > + properties: > + clocks: > + maxItems: 4 Neither here. > + clock-names: > + items: > + - const: aux > + - const: ref > + - const: com_aux Can anyone explain me why do we name these (here and other Qualcomm bindings) based on clock name, not input? Just because different clock is fed to the block, does not necessarily mean the input should be named differently. > + - const: pipe > + > examples: > - | > #include <dt-bindings/clock/qcom,gcc-sc8280xp.h> Best regards, Krzysztof
On 05/04/2023 13:41, Varadarajan Narayanan wrote: > Add dt-bindings for USB3 PHY found on Qualcomm IPQ9574 > > Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com> > --- > Changes in v8: > - Update clock names for ipq9574 > > Changes in v6: > - Made power-domains optional > > Note: In the earlier patch sets, had used the (legacy) > specification available in qcom,msm8996-qmp-usb3-phy.yaml. Moved > to newer specification in qcom,sc8280xp-qmp-usb3-uni-phy.yaml > --- > .../phy/qcom,sc8280xp-qmp-usb3-uni-phy.yaml | 43 +++++++++++++++++++--- > 1 file changed, 37 insertions(+), 6 deletions(-) > > diff --git a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-usb3-uni-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-usb3-uni-phy.yaml > index 16fce10..e902a0d 100644 > --- a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-usb3-uni-phy.yaml > +++ b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-usb3-uni-phy.yaml > @@ -16,6 +16,7 @@ description: > properties: > compatible: > enum: > + - qcom,ipq9574-qmp-usb3-phy > - qcom,sc8280xp-qmp-usb3-uni-phy > > reg: > @@ -25,11 +26,7 @@ properties: > maxItems: 4 > > clock-names: > - items: > - - const: aux > - - const: ref > - - const: com_aux > - - const: pipe > + maxItems: 4 > > power-domains: > maxItems: 1 > @@ -60,7 +57,6 @@ required: > - reg > - clocks > - clock-names > - - power-domains Power domains are required. Commit msg does not explain why this should be now optional. Best regards, Krzysztof
On Thu, Apr 06, 2023 at 09:41:49AM +0200, Krzysztof Kozlowski wrote: > On 05/04/2023 13:41, Varadarajan Narayanan wrote: > > Add dt-bindings for USB3 PHY found on Qualcomm IPQ9574 > > > > Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com> > > --- > > Changes in v8: > > - Update clock names for ipq9574 > > > > Changes in v6: > > - Made power-domains optional > > > > Note: In the earlier patch sets, had used the (legacy) > > specification available in qcom,msm8996-qmp-usb3-phy.yaml. Moved > > to newer specification in qcom,sc8280xp-qmp-usb3-uni-phy.yaml > > --- > > .../phy/qcom,sc8280xp-qmp-usb3-uni-phy.yaml | 43 +++++++++++++++++++--- > > 1 file changed, 37 insertions(+), 6 deletions(-) > > + clock-names: > > + items: > > + - const: aux > > + - const: ref > > + - const: com_aux > > Can anyone explain me why do we name these (here and other Qualcomm > bindings) based on clock name, not input? Just because different clock > is fed to the block, does not necessarily mean the input should be named > differently. I guess part of the answer is that this has just been copied from the vendor dts and (almost) no one but Qualcomm has access to the documentation. What would the input names be here? Also note that there are SoCs that enable both 'cfg_ahb' and 'com_aux' (e.g. sc7180). > > + - const: pipe > > + > > examples: > > - | > > #include <dt-bindings/clock/qcom,gcc-sc8280xp.h> Johan
On Mon, Apr 17, 2023 at 10:05:11AM +0200, Johan Hovold wrote: > On Thu, Apr 06, 2023 at 09:41:49AM +0200, Krzysztof Kozlowski wrote: > > On 05/04/2023 13:41, Varadarajan Narayanan wrote: > > > Add dt-bindings for USB3 PHY found on Qualcomm IPQ9574 > > > > > > Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com> > > > --- > > > Changes in v8: > > > - Update clock names for ipq9574 > > > > > > Changes in v6: > > > - Made power-domains optional > > > > > > Note: In the earlier patch sets, had used the (legacy) > > > specification available in qcom,msm8996-qmp-usb3-phy.yaml. Moved > > > to newer specification in qcom,sc8280xp-qmp-usb3-uni-phy.yaml > > > --- > > > .../phy/qcom,sc8280xp-qmp-usb3-uni-phy.yaml | 43 +++++++++++++++++++--- > > > 1 file changed, 37 insertions(+), 6 deletions(-) > > > > + clock-names: > > > + items: > > > + - const: aux > > > + - const: ref > > > + - const: com_aux > > > > Can anyone explain me why do we name these (here and other Qualcomm > > bindings) based on clock name, not input? Just because different clock > > is fed to the block, does not necessarily mean the input should be named > > differently. > > I guess part of the answer is that this has just been copied from the > vendor dts and (almost) no one but Qualcomm has access to the > documentation. What would the input names be here? > > Also note that there are SoCs that enable both 'cfg_ahb' and 'com_aux' > (e.g. sc7180). The clock name definitions are auto-generated based on the clock tree definitions provided by the h/w team. We followed the naming pattern done in the previous SoCs. Thanks Varada > > > > + - const: pipe > > > + > > > examples: > > > - | > > > #include <dt-bindings/clock/qcom,gcc-sc8280xp.h> > > Johan
On Thu, Apr 06, 2023 at 09:42:31AM +0200, Krzysztof Kozlowski wrote: > On 05/04/2023 13:41, Varadarajan Narayanan wrote: > > Add dt-bindings for USB3 PHY found on Qualcomm IPQ9574 > > > > Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com> > > --- > > Changes in v8: > > - Update clock names for ipq9574 > > > > Changes in v6: > > - Made power-domains optional > > > > Note: In the earlier patch sets, had used the (legacy) > > specification available in qcom,msm8996-qmp-usb3-phy.yaml. Moved > > to newer specification in qcom,sc8280xp-qmp-usb3-uni-phy.yaml > > --- > > .../phy/qcom,sc8280xp-qmp-usb3-uni-phy.yaml | 43 +++++++++++++++++++--- > > 1 file changed, 37 insertions(+), 6 deletions(-) > > > > diff --git a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-usb3-uni-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-usb3-uni-phy.yaml > > index 16fce10..e902a0d 100644 > > --- a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-usb3-uni-phy.yaml > > +++ b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-usb3-uni-phy.yaml > > @@ -16,6 +16,7 @@ description: > > properties: > > compatible: > > enum: > > + - qcom,ipq9574-qmp-usb3-phy > > - qcom,sc8280xp-qmp-usb3-uni-phy > > > > reg: > > @@ -25,11 +26,7 @@ properties: > > maxItems: 4 > > > > clock-names: > > - items: > > - - const: aux > > - - const: ref > > - - const: com_aux > > - - const: pipe > > + maxItems: 4 > > > > power-domains: > > maxItems: 1 > > @@ -60,7 +57,6 @@ required: > > - reg > > - clocks > > - clock-names > > - - power-domains > > Power domains are required. Commit msg does not explain why this should > be now optional. Since IPQ9574 doesn't have power switches couldn't provide power-domains details. So, had to make it optional to pass 'make dtbs_check'. Thanks Varada > Best regards, > Krzysztof >
On 21/04/2023 13:13, Varadarajan Narayanan wrote: > On Thu, Apr 06, 2023 at 09:42:31AM +0200, Krzysztof Kozlowski wrote: >> On 05/04/2023 13:41, Varadarajan Narayanan wrote: >>> Add dt-bindings for USB3 PHY found on Qualcomm IPQ9574 >>> >>> Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com> >>> --- >>> Changes in v8: >>> - Update clock names for ipq9574 >>> >>> Changes in v6: >>> - Made power-domains optional >>> >>> Note: In the earlier patch sets, had used the (legacy) >>> specification available in qcom,msm8996-qmp-usb3-phy.yaml. Moved >>> to newer specification in qcom,sc8280xp-qmp-usb3-uni-phy.yaml >>> --- >>> .../phy/qcom,sc8280xp-qmp-usb3-uni-phy.yaml | 43 +++++++++++++++++++--- >>> 1 file changed, 37 insertions(+), 6 deletions(-) >>> >>> diff --git a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-usb3-uni-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-usb3-uni-phy.yaml >>> index 16fce10..e902a0d 100644 >>> --- a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-usb3-uni-phy.yaml >>> +++ b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-usb3-uni-phy.yaml >>> @@ -16,6 +16,7 @@ description: >>> properties: >>> compatible: >>> enum: >>> + - qcom,ipq9574-qmp-usb3-phy >>> - qcom,sc8280xp-qmp-usb3-uni-phy >>> >>> reg: >>> @@ -25,11 +26,7 @@ properties: >>> maxItems: 4 >>> >>> clock-names: >>> - items: >>> - - const: aux >>> - - const: ref >>> - - const: com_aux >>> - - const: pipe >>> + maxItems: 4 >>> >>> power-domains: >>> maxItems: 1 >>> @@ -60,7 +57,6 @@ required: >>> - reg >>> - clocks >>> - clock-names >>> - - power-domains >> >> Power domains are required. Commit msg does not explain why this should >> be now optional. > > Since IPQ9574 doesn't have power switches couldn't provide power-domains details. > So, had to make it optional to pass 'make dtbs_check'. This should be a part of the commit message, so that the next developer understands your intentions without going to mail archives. > > Thanks > Varada > >> Best regards, >> Krzysztof >>
On 21/04/2023 11:58, Varadarajan Narayanan wrote: > On Mon, Apr 17, 2023 at 10:05:11AM +0200, Johan Hovold wrote: >> On Thu, Apr 06, 2023 at 09:41:49AM +0200, Krzysztof Kozlowski wrote: >>> On 05/04/2023 13:41, Varadarajan Narayanan wrote: >>>> Add dt-bindings for USB3 PHY found on Qualcomm IPQ9574 >>>> >>>> Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com> >>>> --- >>>> Changes in v8: >>>> - Update clock names for ipq9574 >>>> >>>> Changes in v6: >>>> - Made power-domains optional >>>> >>>> Note: In the earlier patch sets, had used the (legacy) >>>> specification available in qcom,msm8996-qmp-usb3-phy.yaml. Moved >>>> to newer specification in qcom,sc8280xp-qmp-usb3-uni-phy.yaml >>>> --- >>>> .../phy/qcom,sc8280xp-qmp-usb3-uni-phy.yaml | 43 +++++++++++++++++++--- >>>> 1 file changed, 37 insertions(+), 6 deletions(-) >> >>>> + clock-names: >>>> + items: >>>> + - const: aux >>>> + - const: ref >>>> + - const: com_aux >>> >>> Can anyone explain me why do we name these (here and other Qualcomm >>> bindings) based on clock name, not input? Just because different clock >>> is fed to the block, does not necessarily mean the input should be named >>> differently. >> >> I guess part of the answer is that this has just been copied from the >> vendor dts and (almost) no one but Qualcomm has access to the >> documentation. What would the input names be here? >> >> Also note that there are SoCs that enable both 'cfg_ahb' and 'com_aux' >> (e.g. sc7180). > > The clock name definitions are auto-generated based on the clock > tree definitions provided by the h/w team. We followed the naming > pattern done in the previous SoCs. Are you sure? We talk about clock inputs here. Best regards, Krzysztof
On Fri, Apr 21, 2023 at 05:19:58PM +0300, Dmitry Baryshkov wrote: > On 21/04/2023 13:13, Varadarajan Narayanan wrote: > >On Thu, Apr 06, 2023 at 09:42:31AM +0200, Krzysztof Kozlowski wrote: > >>On 05/04/2023 13:41, Varadarajan Narayanan wrote: > >>>Add dt-bindings for USB3 PHY found on Qualcomm IPQ9574 > >>> > >>>Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com> > >>>--- > >>> Changes in v8: > >>> - Update clock names for ipq9574 > >>> > >>> Changes in v6: > >>> - Made power-domains optional > >>> > >>>Note: In the earlier patch sets, had used the (legacy) > >>>specification available in qcom,msm8996-qmp-usb3-phy.yaml. Moved > >>>to newer specification in qcom,sc8280xp-qmp-usb3-uni-phy.yaml > >>>--- > >>> .../phy/qcom,sc8280xp-qmp-usb3-uni-phy.yaml | 43 +++++++++++++++++++--- > >>> 1 file changed, 37 insertions(+), 6 deletions(-) > >>> > >>>diff --git a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-usb3-uni-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-usb3-uni-phy.yaml > >>>index 16fce10..e902a0d 100644 > >>>--- a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-usb3-uni-phy.yaml > >>>+++ b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-usb3-uni-phy.yaml > >>>@@ -16,6 +16,7 @@ description: > >>> properties: > >>> compatible: > >>> enum: > >>>+ - qcom,ipq9574-qmp-usb3-phy > >>> - qcom,sc8280xp-qmp-usb3-uni-phy > >>> > >>> reg: > >>>@@ -25,11 +26,7 @@ properties: > >>> maxItems: 4 > >>> > >>> clock-names: > >>>- items: > >>>- - const: aux > >>>- - const: ref > >>>- - const: com_aux > >>>- - const: pipe > >>>+ maxItems: 4 > >>> > >>> power-domains: > >>> maxItems: 1 > >>>@@ -60,7 +57,6 @@ required: > >>> - reg > >>> - clocks > >>> - clock-names > >>>- - power-domains > >> > >>Power domains are required. Commit msg does not explain why this should > >>be now optional. > > > >Since IPQ9574 doesn't have power switches couldn't provide power-domains details. > >So, had to make it optional to pass 'make dtbs_check'. > > This should be a part of the commit message, so that the next developer > understands your intentions without going to mail archives. Thanks for the feedback. Have posted v9 that includes the above in commit message. https://lore.kernel.org/lkml/b00042df41420ac337703ca99ac7876c46552946.1682092324.git.quic_varada@quicinc.com/ Thanks Varada > >>Best regards, > >>Krzysztof > >> > > -- > With best wishes > Dmitry >
diff --git a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-usb3-uni-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-usb3-uni-phy.yaml index 16fce10..e902a0d 100644 --- a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-usb3-uni-phy.yaml +++ b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-usb3-uni-phy.yaml @@ -16,6 +16,7 @@ description: properties: compatible: enum: + - qcom,ipq9574-qmp-usb3-phy - qcom,sc8280xp-qmp-usb3-uni-phy reg: @@ -25,11 +26,7 @@ properties: maxItems: 4 clock-names: - items: - - const: aux - - const: ref - - const: com_aux - - const: pipe + maxItems: 4 power-domains: maxItems: 1 @@ -60,7 +57,6 @@ required: - reg - clocks - clock-names - - power-domains - resets - reset-names - vdda-phy-supply @@ -71,6 +67,41 @@ required: additionalProperties: false +allOf: + - if: + properties: + compatible: + contains: + enum: + - qcom,ipq9574-qmp-usb3-phy + then: + properties: + clocks: + maxItems: 4 + clock-names: + items: + - const: aux + - const: ref + - const: cfg_ahb + - const: pipe + + - if: + properties: + compatible: + contains: + enum: + - qcom,sc8280xp-qmp-usb3-uni-phy + then: + properties: + clocks: + maxItems: 4 + clock-names: + items: + - const: aux + - const: ref + - const: com_aux + - const: pipe + examples: - | #include <dt-bindings/clock/qcom,gcc-sc8280xp.h>