From patchwork Thu Oct 20 18:03:32 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Asutosh Das X-Patchwork-Id: 6335 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:4242:0:0:0:0:0 with SMTP id s2csp251873wrr; Thu, 20 Oct 2022 11:07:37 -0700 (PDT) X-Google-Smtp-Source: AMsMyM548WqGtP4nt9eeT0j4LGk2lQOKTSjp77eyiIVS8NrSAbRCmt84J/d7AD27v3mtbANg9cve X-Received: by 2002:a05:6402:3789:b0:461:3ae6:8d73 with SMTP id et9-20020a056402378900b004613ae68d73mr2129edb.229.1666289256959; Thu, 20 Oct 2022 11:07:36 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1666289256; cv=none; d=google.com; s=arc-20160816; b=P4FHWFnH/uxkDZz/M+4DUBGxhC8TQr17U2syhO6P9M8AU9qd6FYKVZFk1dIyAiYHiW CdVkcWNE1CXvRbU56qUdN1qlcFH7O2NcLFdoghU8ZpSaaKxqxBHVssf6DkfnCbKDlX7H +EH5r+KV1cytz8BG1s7roiYqk8S50qDbbDW8XDw8F3RY/mun49TlhK1KOZbSAUR6njEC hUisDWOI55DvVhS67b5OHL//uMGhauhY9y/IaRBSparSeLYvX3oRQW47Q3mMtO5nAXn2 fJ6pKJJVpw7VyfH1luNR3G57LX5RWdFmBG4X/8aWg892Vsg4mCmqV13S1a+8y+4wab1D oB+w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=gQegGmYVBygW/7LbaZPE4/p5PkXBBNOO7kyOOcrzr1I=; b=0NUoQZLK2nyY6wsOPAwG7e9ayErobfGGjTRlr/Pghe++IzpnOOsYN6BELdxQJ2lHKz fiUySVjMKVN1BssM9WOX/FV0qKxfAtImu0imux/uA8XyT/DK9+0jRsh0d7OC7BHWuRyO W7+GL4GD3U6+SwmMqf31BwBaHY3dLCNLpr5eCwpzFEr5rflD2doq0zaaIyZvVQGJx9oV 08M8u2HY1/331OjeEMBqE3AInj7/9C7VkdWAMivN2ELvt6ICv0LSBeI2jzGbdHC6A5WI /mQTAPmJCpIBOa+dY8wiILcbqmRbEv3MHrrGT1Nk5M7jrxYpZcOPOszVI8sW22SEdUx9 JqxQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b=E7rtYFtf; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id ds1-20020a170907724100b00774d0f10566si18052010ejc.821.2022.10.20.11.07.09; Thu, 20 Oct 2022 11:07:36 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b=E7rtYFtf; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230162AbiJTSGI (ORCPT + 99 others); Thu, 20 Oct 2022 14:06:08 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52532 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230058AbiJTSGD (ORCPT ); Thu, 20 Oct 2022 14:06:03 -0400 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 411C7108261; Thu, 20 Oct 2022 11:05:29 -0700 (PDT) Received: from pps.filterd (m0279862.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.5/8.17.1.5) with ESMTP id 29KBI3i6014478; Thu, 20 Oct 2022 18:05:09 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=qcppdkim1; bh=gQegGmYVBygW/7LbaZPE4/p5PkXBBNOO7kyOOcrzr1I=; b=E7rtYFtfSf21zphxt2uDSP1YSG7+VKA3NrxRmabP7GeCjuWT9mClYSqddmYIlRNqgfJP 5cM62gaY7FDHLLx37hxbT6BewIw6kLrI0BAQQrT77pm63jntAWBMpNGVyx6pNDOE2MfZ 7o2WIneKCKG0NDG52jqjf7z7OX6HKA2OjW3lkAwYhKGNCARc1oMlAjsViQr13Tj4xC+7 q9LXCKu3cds6sSFVblkxvhm01VhwoiAHE2QEGuiCTzsbU4pMptPpXlugJZLnRv38ScxJ NaW6N2bYFt7sCGm8Fvj3Xl0PbhF/9RYdaU3nfGousrMM4EVk8W/VAzjZu1Kg17JT7miU SQ== Received: from nasanppmta02.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3kavfm2dxg-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 20 Oct 2022 18:05:09 +0000 Received: from nasanex01a.na.qualcomm.com (corens_vlan604_snip.qualcomm.com [10.53.140.1]) by NASANPPMTA02.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 29KI58iW031999 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 20 Oct 2022 18:05:08 GMT Received: from asutoshd-linux1.qualcomm.com (10.80.80.8) by nasanex01a.na.qualcomm.com (10.52.223.231) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.29; Thu, 20 Oct 2022 11:05:08 -0700 From: Asutosh Das To: , , CC: , , , , , , , , , , "Asutosh Das" , , Alim Akhtar , "James E.J. Bottomley" , "open list" Subject: [PATCH v3 03/17] ufs: core: Introduce Multi-circular queue capability Date: Thu, 20 Oct 2022 11:03:32 -0700 Message-ID: <1718196085461c37138c194c49146efa5c5503dc.1666288432.git.quic_asutoshd@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: References: MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nasanex01a.na.qualcomm.com (10.52.223.231) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: 0POcqdq33VyLsn9Biasy7DYf6Vz9ZUgF X-Proofpoint-ORIG-GUID: 0POcqdq33VyLsn9Biasy7DYf6Vz9ZUgF X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.895,Hydra:6.0.545,FMLib:17.11.122.1 definitions=2022-10-20_09,2022-10-20_01,2022-06-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 malwarescore=0 spamscore=0 lowpriorityscore=0 priorityscore=1501 mlxlogscore=999 impostorscore=0 bulkscore=0 clxscore=1015 mlxscore=0 adultscore=0 phishscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2209130000 definitions=main-2210200108 X-Spam-Status: No, score=-2.8 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_LOW,SPF_HELO_NONE, SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1747230923736484153?= X-GMAIL-MSGID: =?utf-8?q?1747230923736484153?= Add support to check for MCQ capability in the UFSHC. This capability can be used by host drivers to control MCQ enablement. Co-developed-by: Can Guo Signed-off-by: Can Guo Signed-off-by: Asutosh Das --- drivers/ufs/core/ufshcd.c | 4 ++++ include/ufs/ufshcd.h | 13 +++++++++++++ 2 files changed, 17 insertions(+) diff --git a/drivers/ufs/core/ufshcd.c b/drivers/ufs/core/ufshcd.c index e2be3f4..8d93797 100644 --- a/drivers/ufs/core/ufshcd.c +++ b/drivers/ufs/core/ufshcd.c @@ -2250,6 +2250,10 @@ static inline int ufshcd_hba_capabilities(struct ufs_hba *hba) if (err) dev_err(hba->dev, "crypto setup failed\n"); + hba->mcq_sup = FIELD_GET(MASK_MCQ_SUPPORT, hba->capabilities); + if (!hba->mcq_sup) + return err; + hba->mcq_capabilities = ufshcd_readl(hba, REG_MCQCAP); hba->ext_iid_sup = FIELD_GET(MASK_EXT_IID_SUPPORT, hba->mcq_capabilities); diff --git a/include/ufs/ufshcd.h b/include/ufs/ufshcd.h index c29f4c8..e779bc6 100644 --- a/include/ufs/ufshcd.h +++ b/include/ufs/ufshcd.h @@ -660,6 +660,12 @@ enum ufshcd_caps { * notification if it is supported by the UFS device. */ UFSHCD_CAP_TEMP_NOTIF = 1 << 11, + + /* + * This capability allows the host controller driver to turn on/off + * MCQ mode. MCQ mode may be used to increase performance. + */ + UFSHCD_CAP_MCQ_EN = 1 << 12, }; struct ufs_hba_variant_params { @@ -820,6 +826,7 @@ struct ufs_hba_monitor { * @complete_put: whether or not to call ufshcd_rpm_put() from inside * ufshcd_resume_complete() * @ext_iid_sup: is EXT_IID is supported by UFSHC + * @mcq_sup: is mcq supported by UFSHC */ struct ufs_hba { void __iomem *mmio_base; @@ -969,8 +976,14 @@ struct ufs_hba { u32 luns_avail; bool complete_put; bool ext_iid_sup; + bool mcq_sup; }; +static inline bool is_mcq_supported(struct ufs_hba *hba) +{ + return hba->mcq_sup && (hba->caps & UFSHCD_CAP_MCQ_EN); +} + /* Returns true if clocks can be gated. Otherwise false */ static inline bool ufshcd_is_clkgating_allowed(struct ufs_hba *hba) {