From patchwork Mon Mar 4 12:15:07 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: tip-bot2 for Thomas Gleixner X-Patchwork-Id: 209521 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7301:fa17:b0:10a:f01:a869 with SMTP id ju23csp1379599dyc; Mon, 4 Mar 2024 04:17:18 -0800 (PST) X-Forwarded-Encrypted: i=3; AJvYcCW52DJQJVzV+kUkX4Rd4kkcmDbQMm9ddXPuyU/TkX5lUpVVJn9kNb3zJEm/WPYjovbblJydGCATejANM7/X8mg8eBC6nQ== X-Google-Smtp-Source: AGHT+IE28gLQoDgaUh6KxfKmIbGh0ufiaW5HtEtRE4xHe0lfNX1HjM5TWuW8LbwT1eOWKgOu/bkf X-Received: by 2002:a67:f588:0:b0:472:6623:2dc3 with SMTP id i8-20020a67f588000000b0047266232dc3mr5554195vso.25.1709554637795; Mon, 04 Mar 2024 04:17:17 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1709554637; cv=pass; d=google.com; s=arc-20160816; b=QQk6sC5Jl4s8VDFhEc0Gr2upIfhMmTXCh3B2h5rwZSFG8BLiD/aVavAc+rDHFbhsho jD1IJSBZwDQ1UXohcJcH7L/eDsGzzONDsobt0nUxJrPXuefPy1xSz5dI9O2bY1dnLttR rG0QHdbV+i25XoC8kr4ezsDuoSTTldh1uikG8sAHgZD7aBJ2mFF7myBMwV81sZSBsZII huylf1w8z9PagwO7pi/RpVT/5/+R1uN+6u7z/fbqBtr5b69pz36yRG9KnMYzVbpW2/VI aXWiROYDRNTfiWPjoi25uq3cIUxZcABd3B+63nkD/zJ04GiErLTmwafM59MFcVXE/SMx kM3w== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:precedence:robot-unsubscribe:robot-id :message-id:mime-version:list-unsubscribe:list-subscribe:list-id :precedence:references:in-reply-to:cc:subject:to:reply-to:sender :from:dkim-signature:dkim-signature:date; bh=geDnCpFgvxB2oKuj16bvG/AKad282wxpMr9/+JHwrUs=; fh=ug+vbjx3hYEyfsB5aHBhxI+u027oSYAUfnsAoBvj5oA=; b=IVqf6QSNibR6DkM/IeEwqs+WYqzadPd7RrqaZj76FJAntIAuMR7s66vvn1OBlp4fuK +LfLOuzHwbSwO/awxwf9wRDX24vkpHhfVhaRSW83+fythaUYmnuxR6iueom25dXP1Jzj eBQOL+z7cBHOXmLMSWHiiW5TJfsZmWxDz5US/s0bYiPB5hC2Ce6G3+Fu5PnI5YFmwySs x1DdsDmJ31IIoiDt6PONSrBvW5+6PYbyxqAEG+97twqLfgwdyPqg7Ihs6vMRMm7AE703 uveX98qbE6peTyI8kEB4V5WFdZX+GDizywRNf7HZLp2xmUniXdmqA/2xsRr3p1p5OB8Y qAKw==; dara=google.com ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=oRLSZpbC; dkim=neutral (no key) header.i=@linutronix.de header.s=2020e; arc=pass (i=1 spf=pass spfdomain=linutronix.de dkim=pass dkdomain=linutronix.de dmarc=pass fromdomain=linutronix.de); spf=pass (google.com: domain of linux-kernel+bounces-90557-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:45d1:ec00::1 as permitted sender) smtp.mailfrom="linux-kernel+bounces-90557-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from ny.mirrors.kernel.org (ny.mirrors.kernel.org. [2604:1380:45d1:ec00::1]) by mx.google.com with ESMTPS id c22-20020a0561023c9600b0047269e0bf5dsi1283232vsv.784.2024.03.04.04.17.17 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 04 Mar 2024 04:17:17 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel+bounces-90557-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:45d1:ec00::1 as permitted sender) client-ip=2604:1380:45d1:ec00::1; Authentication-Results: mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=oRLSZpbC; dkim=neutral (no key) header.i=@linutronix.de header.s=2020e; arc=pass (i=1 spf=pass spfdomain=linutronix.de dkim=pass dkdomain=linutronix.de dmarc=pass fromdomain=linutronix.de); spf=pass (google.com: domain of linux-kernel+bounces-90557-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:45d1:ec00::1 as permitted sender) smtp.mailfrom="linux-kernel+bounces-90557-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from smtp.subspace.kernel.org (wormhole.subspace.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ny.mirrors.kernel.org (Postfix) with ESMTPS id 809561C21610 for ; Mon, 4 Mar 2024 12:17:17 +0000 (UTC) Received: from localhost.localdomain (localhost.localdomain [127.0.0.1]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 80D3D3F9FC; Mon, 4 Mar 2024 12:15:16 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="oRLSZpbC"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="2ppw8y05" Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E7C923D3A4; Mon, 4 Mar 2024 12:15:10 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1709554512; cv=none; b=XLWa6pdahmQjZhV+yCj2xf257nvcjCs1LoLwUS9VSRXH+CDpGCU6W49JKSwZQZsx09DcSY/23FTLWhb/8WrDhSz6itB8VCsrv+aFat3A6QMvKxz6gvwDPGn5g6NQTiYQ4JbwhR/0GvoMvTmjVgL2HsdLPgRl1391Yu8z49zUTiU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1709554512; c=relaxed/simple; bh=O4YPBXk06Z/LswFItKphIK70oMVrjDQkBBmiAgD6Ytg=; h=Date:From:To:Subject:Cc:In-Reply-To:References:MIME-Version: Message-ID:Content-Type; b=AcsCL4nw328GionqmVd70dlvsh3qcJQf5LP2nEHuPk4P2kI8JdXYD3rGpN30hLfNtFXkYIfjD1VcWlfN8T69eGrCmC1mjZ4hg8OVuHFxlHLRX70W7bCm0BBDVFa6Di1BehlbNwyNkBRKlIU220K0wGvDMwB7BRQSGF7fXty6yz0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=oRLSZpbC; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=2ppw8y05; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Date: Mon, 04 Mar 2024 12:15:07 -0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1709554508; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=geDnCpFgvxB2oKuj16bvG/AKad282wxpMr9/+JHwrUs=; b=oRLSZpbCB5QNoPjWYrnk0rPtJeGnZBmnQPIlj2cN64PaNTfLcdCiGPm6H4CXH9Csrfn7yz iSj6FDWAKGQZ+yHbKlq+uenpD6ZOoVFlQKStI0a4kcywgxStbJC1/BoFcz6iXKOI64dzT4 AbuBibodT/n+tbyUnIpwmooIR+IRTQd4SOo4kgxRkA0WW4VfQ0L/XF1eRGBOnkq7/Eh2At LhceOOidUDw1jfpI1BK3SsTJPOqqELgRi5QZeeIpnSnwrjpY1Xrwo9wWMTa7MUmtuc0GCs Xhy78PHPR7G0cSE+qxAMHOAAWkEzroEUoszVG30JbIgoteCJxLXSA0qjmH6SOg== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1709554508; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=geDnCpFgvxB2oKuj16bvG/AKad282wxpMr9/+JHwrUs=; b=2ppw8y05MWorFOd7EMG30tXdeIfn8zEvSZnCKQlTVroWcRXLGmi/H+MfnQ+GMC8OgMcRGm iPotwwRHLnvzCYBg== From: "tip-bot2 for Thomas Gleixner" Sender: tip-bot2@linutronix.de Reply-to: linux-kernel@vger.kernel.org To: linux-tip-commits@vger.kernel.org Subject: [tip: x86/cleanups] x86/msr: Prepare for including into Cc: Thomas Gleixner , Ingo Molnar , x86@kernel.org, linux-kernel@vger.kernel.org In-Reply-To: <20240304005104.454678686@linutronix.de> References: <20240304005104.454678686@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <170955450788.398.5285179242265335833.tip-bot2@tip-bot2> Robot-ID: Robot-Unsubscribe: Contact to get blacklisted from these emails Precedence: bulk X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1792597963567499065 X-GMAIL-MSGID: 1792597963567499065 The following commit has been merged into the x86/cleanups branch of tip: Commit-ID: 154fcf3a788868cb87d8c2e50c0b5b3a2fe89853 Gitweb: https://git.kernel.org/tip/154fcf3a788868cb87d8c2e50c0b5b3a2fe89853 Author: Thomas Gleixner AuthorDate: Mon, 04 Mar 2024 11:12:19 +01:00 Committer: Ingo Molnar CommitterDate: Mon, 04 Mar 2024 12:01:39 +01:00 x86/msr: Prepare for including into To clean up the per CPU insanity of UP which causes sparse to be rightfully unhappy and prevents the usage of the generic per CPU accessors on cpu_info it is necessary to include into . Including into is impossible because it ends up in header dependency hell. The problem is that includes . The inclusion of results in a compile fail where the compiler cannot longer handle an include in which references boot_cpu_data which is defined in . The only reason why is included in are the set/get_debugctlmsr() inlines. They are defined there because is such a nice dump ground for everything. In fact they belong obviously into . Move them to and fix up the resulting damage which is just exposing the reliance on random include chains. Signed-off-by: Thomas Gleixner Signed-off-by: Ingo Molnar Link: https://lore.kernel.org/r/20240304005104.454678686@linutronix.de --- arch/x86/events/intel/core.c | 1 + arch/x86/events/intel/ds.c | 1 + arch/x86/include/asm/debugreg.h | 24 ++++++++++++++++++++++++ arch/x86/include/asm/fsgsbase.h | 2 +- arch/x86/include/asm/processor.h | 22 ---------------------- arch/x86/include/asm/special_insns.h | 4 ++-- arch/x86/kernel/cpu/intel_pconfig.c | 2 ++ arch/x86/kernel/cpu/rdrand.c | 1 + arch/x86/kernel/fpu/bugs.c | 2 ++ arch/x86/kernel/step.c | 2 ++ 10 files changed, 36 insertions(+), 25 deletions(-) diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c index 3804f21..768d141 100644 --- a/arch/x86/events/intel/core.c +++ b/arch/x86/events/intel/core.c @@ -17,6 +17,7 @@ #include #include +#include #include #include #include diff --git a/arch/x86/events/intel/ds.c b/arch/x86/events/intel/ds.c index d49d661..2641ba6 100644 --- a/arch/x86/events/intel/ds.c +++ b/arch/x86/events/intel/ds.c @@ -5,6 +5,7 @@ #include #include +#include #include #include #include diff --git a/arch/x86/include/asm/debugreg.h b/arch/x86/include/asm/debugreg.h index 0cec92c..fdbbbfe 100644 --- a/arch/x86/include/asm/debugreg.h +++ b/arch/x86/include/asm/debugreg.h @@ -5,7 +5,9 @@ #include #include #include + #include +#include DECLARE_PER_CPU(unsigned long, cpu_dr7); @@ -159,4 +161,26 @@ static inline unsigned long amd_get_dr_addr_mask(unsigned int dr) } #endif +static inline unsigned long get_debugctlmsr(void) +{ + unsigned long debugctlmsr = 0; + +#ifndef CONFIG_X86_DEBUGCTLMSR + if (boot_cpu_data.x86 < 6) + return 0; +#endif + rdmsrl(MSR_IA32_DEBUGCTLMSR, debugctlmsr); + + return debugctlmsr; +} + +static inline void update_debugctlmsr(unsigned long debugctlmsr) +{ +#ifndef CONFIG_X86_DEBUGCTLMSR + if (boot_cpu_data.x86 < 6) + return; +#endif + wrmsrl(MSR_IA32_DEBUGCTLMSR, debugctlmsr); +} + #endif /* _ASM_X86_DEBUGREG_H */ diff --git a/arch/x86/include/asm/fsgsbase.h b/arch/x86/include/asm/fsgsbase.h index 35cff5f..9e7e8ca 100644 --- a/arch/x86/include/asm/fsgsbase.h +++ b/arch/x86/include/asm/fsgsbase.h @@ -6,7 +6,7 @@ #ifdef CONFIG_X86_64 -#include +#include /* * Read/write a task's FSBASE or GSBASE. This returns the value that diff --git a/arch/x86/include/asm/processor.h b/arch/x86/include/asm/processor.h index 26620d7..d2ef4f5 100644 --- a/arch/x86/include/asm/processor.h +++ b/arch/x86/include/asm/processor.h @@ -576,28 +576,6 @@ extern void cpu_init(void); extern void cpu_init_exception_handling(void); extern void cr4_init(void); -static inline unsigned long get_debugctlmsr(void) -{ - unsigned long debugctlmsr = 0; - -#ifndef CONFIG_X86_DEBUGCTLMSR - if (boot_cpu_data.x86 < 6) - return 0; -#endif - rdmsrl(MSR_IA32_DEBUGCTLMSR, debugctlmsr); - - return debugctlmsr; -} - -static inline void update_debugctlmsr(unsigned long debugctlmsr) -{ -#ifndef CONFIG_X86_DEBUGCTLMSR - if (boot_cpu_data.x86 < 6) - return; -#endif - wrmsrl(MSR_IA32_DEBUGCTLMSR, debugctlmsr); -} - extern void set_task_blockstep(struct task_struct *task, bool on); /* Boot loader type from the setup header: */ diff --git a/arch/x86/include/asm/special_insns.h b/arch/x86/include/asm/special_insns.h index 48f8dd4..f13df37 100644 --- a/arch/x86/include/asm/special_insns.h +++ b/arch/x86/include/asm/special_insns.h @@ -2,11 +2,11 @@ #ifndef _ASM_X86_SPECIAL_INSNS_H #define _ASM_X86_SPECIAL_INSNS_H - #ifdef __KERNEL__ - #include #include + +#include #include #include diff --git a/arch/x86/kernel/cpu/intel_pconfig.c b/arch/x86/kernel/cpu/intel_pconfig.c index 0771a90..5be2b17 100644 --- a/arch/x86/kernel/cpu/intel_pconfig.c +++ b/arch/x86/kernel/cpu/intel_pconfig.c @@ -7,6 +7,8 @@ * Author: * Kirill A. Shutemov */ +#include +#include #include #include diff --git a/arch/x86/kernel/cpu/rdrand.c b/arch/x86/kernel/cpu/rdrand.c index 26a427f..eeac00d 100644 --- a/arch/x86/kernel/cpu/rdrand.c +++ b/arch/x86/kernel/cpu/rdrand.c @@ -6,6 +6,7 @@ * Authors: Fenghua Yu , * H. Peter Anvin */ +#include #include #include diff --git a/arch/x86/kernel/fpu/bugs.c b/arch/x86/kernel/fpu/bugs.c index a06b876..edbafc5 100644 --- a/arch/x86/kernel/fpu/bugs.c +++ b/arch/x86/kernel/fpu/bugs.c @@ -2,6 +2,8 @@ /* * x86 FPU bug checks: */ +#include + #include #include diff --git a/arch/x86/kernel/step.c b/arch/x86/kernel/step.c index 8e2b255..3e29526 100644 --- a/arch/x86/kernel/step.c +++ b/arch/x86/kernel/step.c @@ -6,7 +6,9 @@ #include #include #include + #include +#include #include unsigned long convert_ip_to_linear(struct task_struct *child, struct pt_regs *regs)