[tip:,x86/core] x86: Increase brk randomness entropy for 64-bit systems

Message ID 170899030090.398.7397849626399402025.tip-bot2@tip-bot2
State New
Headers
Series [tip:,x86/core] x86: Increase brk randomness entropy for 64-bit systems |

Commit Message

tip-bot2 for Thomas Gleixner Feb. 26, 2024, 11:31 p.m. UTC
  The following commit has been merged into the x86/core branch of tip:

Commit-ID:     44c76825d6eefee9eb7ce06c38e1a6632ac7eb7d
Gitweb:        https://git.kernel.org/tip/44c76825d6eefee9eb7ce06c38e1a6632ac7eb7d
Author:        Kees Cook <keescook@chromium.org>
AuthorDate:    Fri, 16 Feb 2024 22:25:43 -08:00
Committer:     Thomas Gleixner <tglx@linutronix.de>
CommitterDate: Tue, 27 Feb 2024 00:23:55 +01:00

x86: Increase brk randomness entropy for 64-bit systems

In commit c1d171a00294 ("x86: randomize brk"), arch_randomize_brk() was
defined to use a 32MB range (13 bits of entropy), but was never increased
when moving to 64-bit. The default arch_randomize_brk() uses 32MB for
32-bit tasks, and 1GB (18 bits of entropy) for 64-bit tasks.

Update x86_64 to match the entropy used by arm64 and other 64-bit
architectures.

Reported-by: y0un9n132@gmail.com
Signed-off-by: Kees Cook <keescook@chromium.org>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Acked-by: Jiri Kosina <jkosina@suse.com>
Closes: https://lore.kernel.org/linux-hardening/CA+2EKTVLvc8hDZc+2Yhwmus=dzOUG5E4gV7ayCbu0MPJTZzWkw@mail.gmail.com/
Link: https://lore.kernel.org/r/20240217062545.1631668-1-keescook@chromium.org
---
 arch/x86/kernel/process.c | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)
  

Patch

diff --git a/arch/x86/kernel/process.c b/arch/x86/kernel/process.c
index ab49ade..45a9d49 100644
--- a/arch/x86/kernel/process.c
+++ b/arch/x86/kernel/process.c
@@ -1030,7 +1030,10 @@  unsigned long arch_align_stack(unsigned long sp)
 
 unsigned long arch_randomize_brk(struct mm_struct *mm)
 {
-	return randomize_page(mm->brk, 0x02000000);
+	if (mmap_is_ia32())
+		return randomize_page(mm->brk, SZ_32M);
+
+	return randomize_page(mm->brk, SZ_1G);
 }
 
 /*