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bh=1D8r4RuM60jwQbf9fJpPwR9KpOjyGBosQSQBTxaT/K0=; b=yLpYQeO33XCcMOOPEOaUYaKt7+3q3ELe8NoBPnbJADCxcaCLqryC5RK952QZS0HF2MEp/d qdwF8IVb2baI7KDQ== From: "tip-bot2 for Changhuang Liang" Sender: tip-bot2@linutronix.de Reply-to: linux-kernel@vger.kernel.org To: linux-tip-commits@vger.kernel.org Subject: [tip: irq/core] dt-bindings: interrupt-controller: Add starfive,jh8100-intc Cc: Changhuang Liang , Thomas Gleixner , Ley Foon Tan , Krzysztof Kozlowski , x86@kernel.org, linux-kernel@vger.kernel.org, maz@kernel.org In-Reply-To: <20240226055025.1669223-2-changhuang.liang@starfivetech.com> References: <20240226055025.1669223-2-changhuang.liang@starfivetech.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <170895680237.398.4321467435072927437.tip-bot2@tip-bot2> Robot-ID: Robot-Unsubscribe: Contact to get blacklisted from these emails Precedence: bulk X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1791941564417354114 X-GMAIL-MSGID: 1791971609672093841 The following commit has been merged into the irq/core branch of tip: Commit-ID: d8c56cea725c4d46dd47fbfb4b35a37e7317ac43 Gitweb: https://git.kernel.org/tip/d8c56cea725c4d46dd47fbfb4b35a37e7317ac43 Author: Changhuang Liang AuthorDate: Sun, 25 Feb 2024 21:50:24 -08:00 Committer: Thomas Gleixner CommitterDate: Mon, 26 Feb 2024 15:09:18 +01:00 dt-bindings: interrupt-controller: Add starfive,jh8100-intc StarFive SoCs like the JH8100 use a interrupt controller. Add a binding for it. Signed-off-by: Changhuang Liang Signed-off-by: Thomas Gleixner Reviewed-by: Ley Foon Tan Reviewed-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20240226055025.1669223-2-changhuang.liang@starfivetech.com --- Documentation/devicetree/bindings/interrupt-controller/starfive,jh8100-intc.yaml | 61 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 61 insertions(+) create mode 100644 Documentation/devicetree/bindings/interrupt-controller/starfive,jh8100-intc.yaml diff --git a/Documentation/devicetree/bindings/interrupt-controller/starfive,jh8100-intc.yaml b/Documentation/devicetree/bindings/interrupt-controller/starfive,jh8100-intc.yaml new file mode 100644 index 0000000..ada5788 --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/starfive,jh8100-intc.yaml @@ -0,0 +1,61 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interrupt-controller/starfive,jh8100-intc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: StarFive External Interrupt Controller + +description: + StarFive SoC JH8100 contain a external interrupt controller. It can be used + to handle high-level input interrupt signals. It also send the output + interrupt signal to RISC-V PLIC. + +maintainers: + - Changhuang Liang + +properties: + compatible: + const: starfive,jh8100-intc + + reg: + maxItems: 1 + + clocks: + description: APB clock for the interrupt controller + maxItems: 1 + + resets: + description: APB reset for the interrupt controller + maxItems: 1 + + interrupts: + maxItems: 1 + + interrupt-controller: true + + "#interrupt-cells": + const: 1 + +required: + - compatible + - reg + - clocks + - resets + - interrupts + - interrupt-controller + - "#interrupt-cells" + +additionalProperties: false + +examples: + - | + interrupt-controller@12260000 { + compatible = "starfive,jh8100-intc"; + reg = <0x12260000 0x10000>; + clocks = <&syscrg_ne 76>; + resets = <&syscrg_ne 13>; + interrupts = <45>; + interrupt-controller; + #interrupt-cells = <1>; + };