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Tue, 12 Dec 2023 12:03:03 -0600 Subject: [PATCH v2 2/2] x86/resctrl: Remove hard-coded memory bandwidth event configuration From: Babu Moger To: , , , , , , CC: , , , , , , , , , , , , , , , , , , , , , , , , Date: Tue, 12 Dec 2023 12:02:25 -0600 Message-ID: <170240414535.760665.1609957728181418569.stgit@bmoger-ubuntu> In-Reply-To: <20231201005720.235639-1-babu.moger@amd.com> References: <20231201005720.235639-1-babu.moger@amd.com> User-Agent: StGit/1.1.dev103+g5369f4c MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000E9D2:EE_|BL1PR12MB5825:EE_ X-MS-Office365-Filtering-Correlation-Id: 63379046-8f51-4837-2ce5-08dbfb3c996a X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: jOtkfbmmOKwwOZyYUfUDpfHOxxoc3UNC1Mly85k7F/1i/5R0KQCm3jYY/VgcckL1trwShOzZU2UFIlvOMFTKaL2yZEBIXPBrtyVyuFdaMWFJBGGh0BjQYfRPBAjqWk/awJtu51BaUmYfwTpBZeTUGXGu4v83vi5zaitIg5NV1KEbK5cFgSnNvYo02wu1A9dpf6hIpYLIScW9ZW9/WYv4U6utwpj0P9jdCjJhRGNT7hoeeMIZLU17BVnfG3mH0ajNmVyPYB8tyLeZDeJD3AxUIRvwL+4zVgKM2PfZc2GDKzKp5sJoDlmHqzm5sXRoaep+N4uK9Uhm98/vH9tcAIRPy//3U3EORrJX7T9CVdKK9FfE7b+txkdvvjutaGHBC5V6tOvd2uKBUaCEjDLGXIsVLH+aDV2Yg25/3cCWuEFzF/ks6m82lZv27O/PuTaYe19gbz5OTVhlK5tipbU+ol0UwA/FCitpJS7CMmI1EvRCvveQbZ5rJH3kbsz/4uBwArlEtXyC7s3yexVmNdX0qEfZ7m+suCiqJfDqFvoa3cUrAUfpvoEGiHoVO3z/pJxZd5O6zWwf7SEUAt+llfmxDordBJZPqoBM4MawNexMItbMMtPs5beOQb7MwkZo01GegGcUuqpQOreVLA1CqQpGRrhE+RQ68c9b2/D04AKxLgGI/9m34zz75oI5sBQKN7W96WHvuqtrFXQjP/bDMjmmec2nDHkrlFpr5YcJJnRpn4xLW7xEG//7bbDgAUfdJHk0EbX+siEZ3uEAQRR8JClW4ocp0+XYEhlegdO4/N1hIkwBdu440r70itRY0uimBRPmTRmj/ercRGcjaOQr+6zrFNLJYg== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230031)(4636009)(7916004)(376002)(136003)(39860400002)(346002)(396003)(230922051799003)(451199024)(1800799012)(64100799003)(186009)(82310400011)(36840700001)(40470700004)(46966006)(8936002)(8676002)(41300700001)(2906002)(4326008)(44832011)(5660300002)(7416002)(33716001)(478600001)(36860700001)(966005)(103116003)(16526019)(426003)(83380400001)(26005)(336012)(40480700001)(47076005)(6666004)(9686003)(82740400003)(54906003)(110136005)(16576012)(316002)(70586007)(70206006)(86362001)(81166007)(356005)(40460700003)(71626019)(36900700001);DIR:OUT;SFP:1101; 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Tue, 12 Dec 2023 10:03:17 -0800 (PST) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1784039110226718051 X-GMAIL-MSGID: 1785100186689147141 If the BMEC (Bandwidth Monitoring Event Configuration) feature is supported, the bandwidth events can be configured. The maximum supported bandwidth bitmask can be determined by following CPUID command. CPUID_Fn80000020_ECX_x03 [Platform QoS Monitoring Bandwidth Event Configuration] Read-only. Reset: 0000_007Fh. Bits Description 31:7 Reserved 6:0 Identifies the bandwidth sources that can be tracked. The bandwidth sources can change with the processor generations. Currently, this information is hard-coded. Remove the hard-coded value and detect using CPUID command. Also print the valid bitmask when the user tries to configure invalid value. The CPUID details are documentation in the PPR listed below [1]. [1] Processor Programming Reference (PPR) Vol 1.1 for AMD Family 19h Model 11h B1 - 55901 Rev 0.25. Fixes: dc2a3e857981 ("x86/resctrl: Add interface to read mbm_total_bytes_config") Link: https://bugzilla.kernel.org/show_bug.cgi?id=206537 Signed-off-by: Babu Moger --- v2: Earlier Sent as a part of ABMC feature. https://lore.kernel.org/lkml/20231201005720.235639-1-babu.moger@amd.com/ But this is not related to ABMC. Sending it separate now. Removed the global resctrl_max_evt_bitmask. Added event_mask as part of the resource. --- arch/x86/kernel/cpu/resctrl/internal.h | 5 ++--- arch/x86/kernel/cpu/resctrl/monitor.c | 6 ++++++ arch/x86/kernel/cpu/resctrl/rdtgroup.c | 18 ++++++++++-------- 3 files changed, 18 insertions(+), 11 deletions(-) diff --git a/arch/x86/kernel/cpu/resctrl/internal.h b/arch/x86/kernel/cpu/resctrl/internal.h index d2979748fae4..3e2f505614d8 100644 --- a/arch/x86/kernel/cpu/resctrl/internal.h +++ b/arch/x86/kernel/cpu/resctrl/internal.h @@ -50,9 +50,6 @@ /* Dirty Victims to All Types of Memory */ #define DIRTY_VICTIMS_TO_ALL_MEM BIT(6) -/* Max event bits supported */ -#define MAX_EVT_CONFIG_BITS GENMASK(6, 0) - struct rdt_fs_context { struct kernfs_fs_context kfc; bool enable_cdpl2; @@ -394,6 +391,7 @@ struct rdt_parse_data { * @msr_update: Function pointer to update QOS MSRs * @mon_scale: cqm counter * mon_scale = occupancy in bytes * @mbm_width: Monitor width, to detect and correct for overflow. + * @event_mask: Max supported event bitmask. * @cdp_enabled: CDP state of this resource * * Members of this structure are either private to the architecture @@ -408,6 +406,7 @@ struct rdt_hw_resource { struct rdt_resource *r); unsigned int mon_scale; unsigned int mbm_width; + unsigned int event_mask; bool cdp_enabled; }; diff --git a/arch/x86/kernel/cpu/resctrl/monitor.c b/arch/x86/kernel/cpu/resctrl/monitor.c index f136ac046851..30bf919edfda 100644 --- a/arch/x86/kernel/cpu/resctrl/monitor.c +++ b/arch/x86/kernel/cpu/resctrl/monitor.c @@ -813,6 +813,12 @@ int __init rdt_get_mon_l3_config(struct rdt_resource *r) return ret; if (rdt_cpu_has(X86_FEATURE_BMEC)) { + u32 eax, ebx, ecx, edx; + + /* Detect list of bandwidth sources that can be tracked */ + cpuid_count(0x80000020, 3, &eax, &ebx, &ecx, &edx); + hw_res->event_mask = ecx; + if (rdt_cpu_has(X86_FEATURE_CQM_MBM_TOTAL)) { mbm_total_event.configurable = true; mbm_config_rftype_init("mbm_total_bytes_config"); diff --git a/arch/x86/kernel/cpu/resctrl/rdtgroup.c b/arch/x86/kernel/cpu/resctrl/rdtgroup.c index 69a1de92384a..8a1e9fdab974 100644 --- a/arch/x86/kernel/cpu/resctrl/rdtgroup.c +++ b/arch/x86/kernel/cpu/resctrl/rdtgroup.c @@ -1537,17 +1537,14 @@ static void mon_event_config_read(void *info) { struct mon_config_info *mon_info = info; unsigned int index; - u64 msrval; + u32 h; index = mon_event_config_index_get(mon_info->evtid); if (index == INVALID_CONFIG_INDEX) { pr_warn_once("Invalid event id %d\n", mon_info->evtid); return; } - rdmsrl(MSR_IA32_EVT_CFG_BASE + index, msrval); - - /* Report only the valid event configuration bits */ - mon_info->mon_config = msrval & MAX_EVT_CONFIG_BITS; + rdmsr(MSR_IA32_EVT_CFG_BASE + index, mon_info->mon_config, h); } static void mondata_config_read(struct rdt_domain *d, struct mon_config_info *mon_info) @@ -1557,6 +1554,7 @@ static void mondata_config_read(struct rdt_domain *d, struct mon_config_info *mo static int mbm_config_show(struct seq_file *s, struct rdt_resource *r, u32 evtid) { + struct rdt_hw_resource *hw_res = resctrl_to_arch_res(r); struct mon_config_info mon_info = {0}; struct rdt_domain *dom; bool sep = false; @@ -1571,7 +1569,9 @@ static int mbm_config_show(struct seq_file *s, struct rdt_resource *r, u32 evtid mon_info.evtid = evtid; mondata_config_read(dom, &mon_info); - seq_printf(s, "%d=0x%02x", dom->id, mon_info.mon_config); + /* Report only the valid event configuration bits */ + seq_printf(s, "%d=0x%02x", dom->id, + mon_info.mon_config & hw_res->event_mask); sep = true; } seq_puts(s, "\n"); @@ -1617,12 +1617,14 @@ static void mon_event_config_write(void *info) static int mbm_config_write_domain(struct rdt_resource *r, struct rdt_domain *d, u32 evtid, u32 val) { + struct rdt_hw_resource *hw_res = resctrl_to_arch_res(r); struct mon_config_info mon_info = {0}; int ret = 0; /* mon_config cannot be more than the supported set of events */ - if (val > MAX_EVT_CONFIG_BITS) { - rdt_last_cmd_puts("Invalid event configuration\n"); + if ((val & hw_res->event_mask) != val) { + rdt_last_cmd_printf("Invalid input: The maximum valid bitmask is 0x%02x\n", + hw_res->event_mask); return -EINVAL; }