From patchwork Tue Dec 12 14:44:22 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: tip-bot2 for Thomas Gleixner X-Patchwork-Id: 177385 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:bcd1:0:b0:403:3b70:6f57 with SMTP id r17csp7769354vqy; Tue, 12 Dec 2023 06:44:53 -0800 (PST) X-Google-Smtp-Source: AGHT+IHl7o0n9qOMrON/Jy3akGa7R1w3KJaywRNEvPFJNAidqpPNskztO9xIJAUxMyaAyOc3ub9I X-Received: by 2002:a17:902:654a:b0:1d3:4749:c75c with SMTP id d10-20020a170902654a00b001d34749c75cmr125934pln.130.1702392292796; Tue, 12 Dec 2023 06:44:52 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1702392292; cv=none; d=google.com; s=arc-20160816; b=NtwUww23UyBq1wRiyLJKMafefaGQQH5MF52p3skhyzXkcVicn8NoEC1QlVF6F9af2e LGWB3pM4g0bPwc9GA3N7PQeZG92pzOqdtxz6vWLWAb4H+3BUM7mXYrzP2AK42XVGm24b 5L0cDVYyXN+kDaPgtrGkAiSTs+mrS/RoR29u5QX2ryEG8R1nWo4JPY7uwCZEIhDYtwX9 Vx2y47iD5x7pMsrCsZLgRaqNT5iuihGXAekyGICKOIsRYwxlIZ5xueNOmG0HPck8PiW8 lZEGLBJeKWmF6IsGDFJMWJwTD+jS5LIkji9sHxzSAsPgeI7H7KPnKpnO9gKKd7Z7Yvhd q3Hw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:robot-unsubscribe :robot-id:message-id:mime-version:references:in-reply-to:cc:subject :to:reply-to:sender:from:dkim-signature:dkim-signature:date; bh=2ie1W9GDcWrrhjsxjTMzRGHh5hSWMkXx9vnEx2J0UWI=; fh=I2NWj4QewUsJB8D1FIavcvdqna0ckJ8Bw6HOcWrZ4cM=; b=IUGyv4FxaqCfy3RA8GgRQTwborIuMWVDqsjG5YKf2529LLISbBrX8t8TGXPnYD6UNd yrFwcI2vDot9Y6lu4VAHdmtYoRtQJ6ualJ/MFE5K4gSLLJk8c2JL3LYDTytpAiKHbfIG QhVZ4hNb3MULB475rvhqeYNPKplMBfkk8hC6ubqpBM6a1wKM9L5T35Fh8Y/268vDKyA+ rET5vrcOsAh4e/2RV/QmbKAdEeRUbu44TWToKGYTlMYftroMUInPD26J9Z/UGVfWAOYf fzqAV+3D1BF+Z5/ZlZVXs/GuGsepD782P6tkV2obDmfbNNhKKcLG01SDPYhO+RF2ouHR OPdg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=UH6ZpqBo; dkim=neutral (no key) header.i=@linutronix.de header.b=0Ij3XX2q; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.38 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from fry.vger.email (fry.vger.email. [23.128.96.38]) by mx.google.com with ESMTPS id y8-20020a17090322c800b001cfb316a183si8047001plg.141.2023.12.12.06.44.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 12 Dec 2023 06:44:52 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.38 as permitted sender) client-ip=23.128.96.38; Authentication-Results: mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=UH6ZpqBo; dkim=neutral (no key) header.i=@linutronix.de header.b=0Ij3XX2q; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.38 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by fry.vger.email (Postfix) with ESMTP id 64CA680A2375; Tue, 12 Dec 2023 06:44:40 -0800 (PST) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.11 at fry.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1376923AbjLLOo2 (ORCPT + 99 others); Tue, 12 Dec 2023 09:44:28 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43450 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1376897AbjLLOoS (ORCPT ); Tue, 12 Dec 2023 09:44:18 -0500 Received: from galois.linutronix.de (Galois.linutronix.de [IPv6:2a0a:51c0:0:12e:550::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E96BAA8; Tue, 12 Dec 2023 06:44:24 -0800 (PST) Date: Tue, 12 Dec 2023 14:44:22 -0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1702392263; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=2ie1W9GDcWrrhjsxjTMzRGHh5hSWMkXx9vnEx2J0UWI=; b=UH6ZpqBooAefwAafNfYZSfaIUonubBjb00I5CUANyik50PNtijCUXomj5ZttBm4UVcCnKp 4dH2GdIp1ozev10UzphAMGLnndpuQqCDk2f35KcZhzFTf4UshwbmDOTLzTAY5EJww/V5SN ncDnncrfMii2qtGrU91p14226EwYU6vT0UYCa7hhr3Wb7mD6hpjrOeGMAc26PZNbOCxKpw 7AaPwCskz68l47Hksy3RdsQBq6POEj58oVh1sVz7miTDHO0QWexCZicIg7Bc17q/HgX0vm ci/o7Z1WQwbdhQpHkizoDwk68337t4iHRwd3555zjugaZf6Xxg45ItPlxUQAmA== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1702392263; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=2ie1W9GDcWrrhjsxjTMzRGHh5hSWMkXx9vnEx2J0UWI=; b=0Ij3XX2qxEzisscW3WjpY1TZS4bE9jjJbxPLkBsKXwzQPOh/la2dvqwMQ4mZqrF55KVo0v iDeY0JsR5TFJicBQ== From: "tip-bot2 for Claudiu Beznea" Sender: tip-bot2@linutronix.de Reply-to: linux-kernel@vger.kernel.org To: linux-tip-commits@vger.kernel.org Subject: [tip: irq/core] irqchip/renesas-rzg2l: Add macro to retrieve TITSR register offset based on register's index Cc: Claudiu Beznea , Thomas Gleixner , x86@kernel.org, linux-kernel@vger.kernel.org, maz@kernel.org In-Reply-To: <20231120111820.87398-7-claudiu.beznea.uj@bp.renesas.com> References: <20231120111820.87398-7-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 Message-ID: <170239226285.398.17559475715941394376.tip-bot2@tip-bot2> Robot-ID: Robot-Unsubscribe: Contact to get blacklisted from these emails X-Spam-Status: No, score=-0.9 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on fry.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (fry.vger.email [0.0.0.0]); Tue, 12 Dec 2023 06:44:40 -0800 (PST) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1783169247245157163 X-GMAIL-MSGID: 1785087700607495022 The following commit has been merged into the irq/core branch of tip: Commit-ID: 2eca4731cc66563b3919d8753dbd74d18c39f662 Gitweb: https://git.kernel.org/tip/2eca4731cc66563b3919d8753dbd74d18c39f662 Author: Claudiu Beznea AuthorDate: Mon, 20 Nov 2023 13:18:17 +02:00 Committer: Thomas Gleixner CommitterDate: Tue, 12 Dec 2023 15:40:41 +01:00 irqchip/renesas-rzg2l: Add macro to retrieve TITSR register offset based on register's index There are 2 TITSR registers available on the IA55 interrupt controller. Add a macro that retrieves the TITSR register offset based on it's index. This macro is useful in when adding suspend/resume support so both TITSR registers can be accessed in a for loop. Signed-off-by: Claudiu Beznea Signed-off-by: Thomas Gleixner Link: https://lore.kernel.org/r/20231120111820.87398-7-claudiu.beznea.uj@bp.renesas.com --- drivers/irqchip/irq-renesas-rzg2l.c | 14 ++++++-------- 1 file changed, 6 insertions(+), 8 deletions(-) diff --git a/drivers/irqchip/irq-renesas-rzg2l.c b/drivers/irqchip/irq-renesas-rzg2l.c index d450417..34add75 100644 --- a/drivers/irqchip/irq-renesas-rzg2l.c +++ b/drivers/irqchip/irq-renesas-rzg2l.c @@ -28,8 +28,7 @@ #define ISCR 0x10 #define IITSR 0x14 #define TSCR 0x20 -#define TITSR0 0x24 -#define TITSR1 0x28 +#define TITSR(n) (0x24 + (n) * 4) #define TITSR0_MAX_INT 16 #define TITSEL_WIDTH 0x2 #define TSSR(n) (0x30 + ((n) * 4)) @@ -200,8 +199,7 @@ static int rzg2l_tint_set_edge(struct irq_data *d, unsigned int type) struct rzg2l_irqc_priv *priv = irq_data_to_priv(d); unsigned int hwirq = irqd_to_hwirq(d); u32 titseln = hwirq - IRQC_TINT_START; - u32 offset; - u8 sense; + u8 index, sense; u32 reg; switch (type & IRQ_TYPE_SENSE_MASK) { @@ -217,17 +215,17 @@ static int rzg2l_tint_set_edge(struct irq_data *d, unsigned int type) return -EINVAL; } - offset = TITSR0; + index = 0; if (titseln >= TITSR0_MAX_INT) { titseln -= TITSR0_MAX_INT; - offset = TITSR1; + index = 1; } raw_spin_lock(&priv->lock); - reg = readl_relaxed(priv->base + offset); + reg = readl_relaxed(priv->base + TITSR(index)); reg &= ~(IRQ_MASK << (titseln * TITSEL_WIDTH)); reg |= sense << (titseln * TITSEL_WIDTH); - writel_relaxed(reg, priv->base + offset); + writel_relaxed(reg, priv->base + TITSR(index)); raw_spin_unlock(&priv->lock); return 0;