From patchwork Tue Dec 12 10:33:17 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: tip-bot2 for Thomas Gleixner X-Patchwork-Id: 177229 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:bcd1:0:b0:403:3b70:6f57 with SMTP id r17csp7631032vqy; Tue, 12 Dec 2023 02:33:26 -0800 (PST) X-Google-Smtp-Source: AGHT+IF1t9sYzq2VY12irgV85GzD3opc+qczZkacaP+R5+l2GcxfRVtwR9u6sKhBicq6p10pYUBO X-Received: by 2002:a05:6808:1886:b0:3b8:b063:8257 with SMTP id bi6-20020a056808188600b003b8b0638257mr6815596oib.89.1702377206022; Tue, 12 Dec 2023 02:33:26 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1702377205; cv=none; d=google.com; s=arc-20160816; b=J5OErHbtHeiRyNeE+F7sxBT49boLduFlF4EOni78ZGyVSeTZsxLXBfA1LmrSDqzZiu krDpOUDuK/u/Ic6y5DZChKaS49Vwla3727foMHYQDb40Cdp25rsr5ytBCxLBF/B4Onch zYr9SFbF5dUeKyGdz+M3BSGPrqC1854SC8GOTsQS1r764lnnV0AR5dT3pUHemtgjb/l6 1ggHPlnK80+afRwbAgrI/XF2pjm4Sj9Kkc+rzeKOiriqnJkD13v2i3ZEbHW45GGlguSy zxM55jSkSS4eDVS/J5V53jDRoMONXtZAd4Cmw6adpUwmdLDGHOtOnZ/CaieA6n/YciBk HmmA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:robot-unsubscribe :robot-id:message-id:mime-version:references:in-reply-to:cc:subject :to:reply-to:sender:from:dkim-signature:dkim-signature:date; bh=+a2nGAgihtQNR6oAJmNTsSqLsllRV9xD2+EzyHqLHp0=; fh=tvZByeGfZUC3GlZS9i7trn4GKZXNMKRjFOkNsWQ3mlI=; b=WuQuk0BEdcsCmmPbxnEFpT5UDJ/7kPrQXqVKI0cXCpUPoXN6GVjziNRZu7bzNz3cPW IJ1vKX0lShBUdIUtTN4e/KSH6OyHrXBqVUxs8WIZOOs9uEZroGuY+iNINw2fT8FldCKW X6k1QisFpoYtBtbowaitezmXO3r6cI1ZzuSaz/82aZqnwqcgADtX6asW/WvPO/6araqp XnD/TY2dvbn2Dxh1S7SjljJ1W86fHiBP2Rl5Yr8ToaXcq7kj3kTWU94WcQszZIHkZHuH CXI6OhAMNTlBETXm+Yxa3vqZFaCOM5yktO/jpfRsxcmFPASCOaKEtThOAXgoZP2viUHa 1YFQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=3KwgS6TH; dkim=neutral (no key) header.i=@linutronix.de header.s=2020e; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:7 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from snail.vger.email (snail.vger.email. [2620:137:e000::3:7]) by mx.google.com with ESMTPS id c22-20020a056a000ad600b006ce5357405fsi7569296pfl.9.2023.12.12.02.33.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 12 Dec 2023 02:33:25 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:7 as permitted sender) client-ip=2620:137:e000::3:7; Authentication-Results: mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=3KwgS6TH; dkim=neutral (no key) header.i=@linutronix.de header.s=2020e; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:7 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by snail.vger.email (Postfix) with ESMTP id DCF0E80A184C; Tue, 12 Dec 2023 02:33:24 -0800 (PST) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.11 at snail.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232437AbjLLKdP (ORCPT + 99 others); Tue, 12 Dec 2023 05:33:15 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53366 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232400AbjLLKdO (ORCPT ); Tue, 12 Dec 2023 05:33:14 -0500 Received: from galois.linutronix.de (Galois.linutronix.de [IPv6:2a0a:51c0:0:12e:550::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 259BAA6; Tue, 12 Dec 2023 02:33:20 -0800 (PST) Date: Tue, 12 Dec 2023 10:33:17 -0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1702377198; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=+a2nGAgihtQNR6oAJmNTsSqLsllRV9xD2+EzyHqLHp0=; b=3KwgS6THwNO5qsR1XlqzEDMeWxmfnhHBw6JGgYoe4TPVGNsOH1PZHS4mNF47fnd2PqkUOv tmeUvqrVWdSm4a+j5StACC0AtSIokNPf2KYFcprZFKDwYW+S2hXd4YshaoLWIFqMARkwjj LlBMSMIQntdpoKU3NFWk8VvDlsX4jD0+sMm+EVNRR1KQnwTSXshQhFlbtaVzu/PBEIVgBl lpP7iaj4ZE+pJpfaaBmgzE8WGKyY/BME+LJpOJEIszUTFrHWs2GrdHwAHqBN3z5EUrOQnP I64lurAbMO9sB/x49dOq3H5JJKkGtCfqvE8PXhSks16oSXpNwplkMOrAbtfN5w== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1702377198; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=+a2nGAgihtQNR6oAJmNTsSqLsllRV9xD2+EzyHqLHp0=; b=cJuygFpDB8+tgVqMRDy8xfDhU7iRjm/eEUFUKUXwwgu6PSnEykqcbUt8qjSpIRtXaI3iWV 1ECAUazdr4J3v7BA== From: "tip-bot2 for Borislav Petkov (AMD)" Sender: tip-bot2@linutronix.de Reply-to: linux-kernel@vger.kernel.org To: linux-tip-commits@vger.kernel.org Subject: [tip: x86/cpu] x86/CPU/AMD: Add X86_FEATURE_ZEN1 Cc: Brian Gerst , Tom Lendacky , "Borislav Petkov (AMD)" , x86@kernel.org, linux-kernel@vger.kernel.org In-Reply-To: References: MIME-Version: 1.0 Message-ID: <170237719725.398.5191492346336231574.tip-bot2@tip-bot2> Robot-ID: Robot-Unsubscribe: Contact to get blacklisted from these emails X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (snail.vger.email [0.0.0.0]); Tue, 12 Dec 2023 02:33:25 -0800 (PST) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1784188432696247720 X-GMAIL-MSGID: 1785071881161821496 The following commit has been merged into the x86/cpu branch of tip: Commit-ID: 232afb557835d6f6859c73bf610bad308c96b131 Gitweb: https://git.kernel.org/tip/232afb557835d6f6859c73bf610bad308c96b131 Author: Borislav Petkov (AMD) AuthorDate: Sat, 02 Dec 2023 12:50:23 +01:00 Committer: Borislav Petkov (AMD) CommitterDate: Tue, 12 Dec 2023 11:17:37 +01:00 x86/CPU/AMD: Add X86_FEATURE_ZEN1 Add a synthetic feature flag specifically for first generation Zen machines. There's need to have a generic flag for all Zen generations so make X86_FEATURE_ZEN be that flag. Fixes: 30fa92832f40 ("x86/CPU/AMD: Add ZenX generations flags") Suggested-by: Brian Gerst Suggested-by: Tom Lendacky Signed-off-by: Borislav Petkov (AMD) Link: https://lore.kernel.org/r/dc3835e3-0731-4230-bbb9-336bbe3d042b@amd.com --- arch/x86/include/asm/cpufeatures.h | 3 ++- arch/x86/kernel/cpu/amd.c | 11 ++++++----- tools/arch/x86/include/asm/cpufeatures.h | 2 +- 3 files changed, 9 insertions(+), 7 deletions(-) diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h index 149cc5d..632c26c 100644 --- a/arch/x86/include/asm/cpufeatures.h +++ b/arch/x86/include/asm/cpufeatures.h @@ -218,7 +218,7 @@ #define X86_FEATURE_IBRS ( 7*32+25) /* Indirect Branch Restricted Speculation */ #define X86_FEATURE_IBPB ( 7*32+26) /* Indirect Branch Prediction Barrier */ #define X86_FEATURE_STIBP ( 7*32+27) /* Single Thread Indirect Branch Predictors */ -#define X86_FEATURE_ZEN ( 7*32+28) /* "" CPU based on Zen microarchitecture */ +#define X86_FEATURE_ZEN ( 7*32+28) /* "" Generic flag for all Zen and newer */ #define X86_FEATURE_L1TF_PTEINV ( 7*32+29) /* "" L1TF workaround PTE inversion */ #define X86_FEATURE_IBRS_ENHANCED ( 7*32+30) /* Enhanced IBRS */ #define X86_FEATURE_MSR_IA32_FEAT_CTL ( 7*32+31) /* "" MSR IA32_FEAT_CTL configured */ @@ -315,6 +315,7 @@ #define X86_FEATURE_ZEN2 (11*32+28) /* "" CPU based on Zen2 microarchitecture */ #define X86_FEATURE_ZEN3 (11*32+29) /* "" CPU based on Zen3 microarchitecture */ #define X86_FEATURE_ZEN4 (11*32+30) /* "" CPU based on Zen4 microarchitecture */ +#define X86_FEATURE_ZEN1 (11*32+31) /* "" CPU based on Zen1 microarchitecture */ /* Intel-defined CPU features, CPUID level 0x00000007:1 (EAX), word 12 */ #define X86_FEATURE_AVX_VNNI (12*32+ 4) /* AVX VNNI instructions */ diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c index 89bbb1a..3395863 100644 --- a/arch/x86/kernel/cpu/amd.c +++ b/arch/x86/kernel/cpu/amd.c @@ -542,7 +542,7 @@ static void bsp_init_amd(struct cpuinfo_x86 *c) switch (c->x86_model) { case 0x00 ... 0x2f: case 0x50 ... 0x5f: - setup_force_cpu_cap(X86_FEATURE_ZEN); + setup_force_cpu_cap(X86_FEATURE_ZEN1); break; case 0x30 ... 0x4f: case 0x60 ... 0x7f: @@ -948,12 +948,13 @@ void init_spectral_chicken(struct cpuinfo_x86 *c) static void init_amd_zen_common(void) { + setup_force_cpu_cap(X86_FEATURE_ZEN); #ifdef CONFIG_NUMA node_reclaim_distance = 32; #endif } -static void init_amd_zen(struct cpuinfo_x86 *c) +static void init_amd_zen1(struct cpuinfo_x86 *c) { init_amd_zen_common(); fix_erratum_1386(c); @@ -1075,8 +1076,8 @@ static void init_amd(struct cpuinfo_x86 *c) case 0x16: init_amd_jg(c); break; } - if (boot_cpu_has(X86_FEATURE_ZEN)) - init_amd_zen(c); + if (boot_cpu_has(X86_FEATURE_ZEN1)) + init_amd_zen1(c); else if (boot_cpu_has(X86_FEATURE_ZEN2)) init_amd_zen2(c); else if (boot_cpu_has(X86_FEATURE_ZEN3)) @@ -1143,7 +1144,7 @@ static void init_amd(struct cpuinfo_x86 *c) * Counter May Be Inaccurate". */ if (cpu_has(c, X86_FEATURE_IRPERF) && - (boot_cpu_has(X86_FEATURE_ZEN) && c->x86_model > 0x2f)) + (boot_cpu_has(X86_FEATURE_ZEN1) && c->x86_model > 0x2f)) msr_set_bit(MSR_K7_HWCR, MSR_K7_HWCR_IRPERF_EN_BIT); check_null_seg_clears_base(c); diff --git a/tools/arch/x86/include/asm/cpufeatures.h b/tools/arch/x86/include/asm/cpufeatures.h index 798e60b..845a402 100644 --- a/tools/arch/x86/include/asm/cpufeatures.h +++ b/tools/arch/x86/include/asm/cpufeatures.h @@ -219,7 +219,7 @@ #define X86_FEATURE_IBRS ( 7*32+25) /* Indirect Branch Restricted Speculation */ #define X86_FEATURE_IBPB ( 7*32+26) /* Indirect Branch Prediction Barrier */ #define X86_FEATURE_STIBP ( 7*32+27) /* Single Thread Indirect Branch Predictors */ -#define X86_FEATURE_ZEN (7*32+28) /* "" CPU based on Zen microarchitecture */ +#define X86_FEATURE_ZEN ( 7*32+28) /* "" Generic flag for all Zen and newer */ #define X86_FEATURE_L1TF_PTEINV ( 7*32+29) /* "" L1TF workaround PTE inversion */ #define X86_FEATURE_IBRS_ENHANCED ( 7*32+30) /* Enhanced IBRS */ #define X86_FEATURE_MSR_IA32_FEAT_CTL ( 7*32+31) /* "" MSR IA32_FEAT_CTL configured */