Message ID | 1700702093-8008-1-git-send-email-shengjiu.wang@nxp.com |
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State | New |
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[23.128.96.32]) by mx.google.com with ESMTPS id p11-20020a170902e74b00b001c7845637efsi154954plf.488.2023.11.22.17.56.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 22 Nov 2023 17:56:02 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.32 as permitted sender) client-ip=23.128.96.32; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.32 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=nxp.com Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by agentk.vger.email (Postfix) with ESMTP id 20B1E822157B; Wed, 22 Nov 2023 17:55:53 -0800 (PST) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.11 at agentk.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1343882AbjKWBzQ (ORCPT <rfc822;ouuuleilei@gmail.com> + 99 others); Wed, 22 Nov 2023 20:55:16 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42440 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1344458AbjKWBzJ (ORCPT <rfc822;linux-kernel@vger.kernel.org>); Wed, 22 Nov 2023 20:55:09 -0500 Received: from inva021.nxp.com (inva021.nxp.com [92.121.34.21]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id F279F10F6 for <linux-kernel@vger.kernel.org>; Wed, 22 Nov 2023 17:55:08 -0800 (PST) Received: from inva021.nxp.com (localhost [127.0.0.1]) by inva021.eu-rdc02.nxp.com (Postfix) with ESMTP id 9306D2001BE; Thu, 23 Nov 2023 02:55:07 +0100 (CET) Received: from aprdc01srsp001v.ap-rdc01.nxp.com (aprdc01srsp001v.ap-rdc01.nxp.com [165.114.16.16]) by inva021.eu-rdc02.nxp.com (Postfix) with ESMTP id 65DCC200FF2; Thu, 23 Nov 2023 02:55:07 +0100 (CET) Received: from localhost.localdomain (shlinux2.ap.freescale.net [10.192.224.44]) by aprdc01srsp001v.ap-rdc01.nxp.com (Postfix) with ESMTP id 30C83181D0E5; Thu, 23 Nov 2023 09:55:06 +0800 (+08) From: Shengjiu Wang <shengjiu.wang@nxp.com> To: nicoleotsuka@gmail.com, Xiubo.Lee@gmail.com, festevam@gmail.com, shengjiu.wang@gmail.com, lgirdwood@gmail.com, broonie@kernel.org, perex@perex.cz, tiwai@suse.com, alsa-devel@alsa-project.org Cc: linuxppc-dev@lists.ozlabs.org, linux-kernel@vger.kernel.org Subject: [PATCH] ASoC: fsl_xcvr: refine the requested phy clock frequency Date: Thu, 23 Nov 2023 09:14:53 +0800 Message-Id: <1700702093-8008-1-git-send-email-shengjiu.wang@nxp.com> X-Mailer: git-send-email 2.7.4 X-Virus-Scanned: ClamAV using ClamSMTP X-Spam-Status: No, score=-0.8 required=5.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on agentk.vger.email Precedence: bulk List-ID: <linux-kernel.vger.kernel.org> X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (agentk.vger.email [0.0.0.0]); Wed, 22 Nov 2023 17:55:53 -0800 (PST) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1783317986949543149 X-GMAIL-MSGID: 1783317986949543149 |
Series |
ASoC: fsl_xcvr: refine the requested phy clock frequency
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Commit Message
Shengjiu Wang
Nov. 23, 2023, 1:14 a.m. UTC
As the input phy clock frequency will divided by 2 by default
on i.MX8MP with the implementation of clk-imx8mp-audiomix driver,
So the requested frequency need to be updated.
The relation of phy clock is:
sai_pll_ref_sel
sai_pll
sai_pll_bypass
sai_pll_out
sai_pll_out_div2
earc_phy_cg
Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
---
sound/soc/fsl/fsl_xcvr.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
Comments
On 11/23/2023 3:14 AM, Shengjiu Wang wrote: > As the input phy clock frequency will divided by 2 by default > on i.MX8MP with the implementation of clk-imx8mp-audiomix driver, > So the requested frequency need to be updated. > > The relation of phy clock is: > sai_pll_ref_sel > sai_pll > sai_pll_bypass > sai_pll_out > sai_pll_out_div2 > earc_phy_cg > > Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com> Reviewed-by: Iuliana Prodan <iuliana.prodan@nxp.com> Thanks, Iulia > --- > sound/soc/fsl/fsl_xcvr.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/sound/soc/fsl/fsl_xcvr.c b/sound/soc/fsl/fsl_xcvr.c > index 77f8e2394bf9..f0fb33d719c2 100644 > --- a/sound/soc/fsl/fsl_xcvr.c > +++ b/sound/soc/fsl/fsl_xcvr.c > @@ -358,7 +358,7 @@ static int fsl_xcvr_en_aud_pll(struct fsl_xcvr *xcvr, u32 freq) > struct device *dev = &xcvr->pdev->dev; > int ret; > > - freq = xcvr->soc_data->spdif_only ? freq / 10 : freq; > + freq = xcvr->soc_data->spdif_only ? freq / 5 : freq; > clk_disable_unprepare(xcvr->phy_clk); > ret = clk_set_rate(xcvr->phy_clk, freq); > if (ret < 0) { > @@ -409,7 +409,7 @@ static int fsl_xcvr_prepare(struct snd_pcm_substream *substream, > bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK; > u32 m_ctl = 0, v_ctl = 0; > u32 r = substream->runtime->rate, ch = substream->runtime->channels; > - u32 fout = 32 * r * ch * 10 * 2; > + u32 fout = 32 * r * ch * 10; > int ret = 0; > > switch (xcvr->mode) {
On Thu, 23 Nov 2023 09:14:53 +0800, Shengjiu Wang wrote: > As the input phy clock frequency will divided by 2 by default > on i.MX8MP with the implementation of clk-imx8mp-audiomix driver, > So the requested frequency need to be updated. > > The relation of phy clock is: > sai_pll_ref_sel > sai_pll > sai_pll_bypass > sai_pll_out > sai_pll_out_div2 > earc_phy_cg > > [...] Applied to https://git.kernel.org/pub/scm/linux/kernel/git/broonie/sound.git for-next Thanks! [1/1] ASoC: fsl_xcvr: refine the requested phy clock frequency commit: 347ecf29a68cc8958fbcbd26ef410d07fe9d82f4 All being well this means that it will be integrated into the linux-next tree (usually sometime in the next 24 hours) and sent to Linus during the next merge window (or sooner if it is a bug fix), however if problems are discovered then the patch may be dropped or reverted. You may get further e-mails resulting from automated or manual testing and review of the tree, please engage with people reporting problems and send followup patches addressing any issues that are reported if needed. If any updates are required or you are submitting further changes they should be sent as incremental updates against current git, existing patches will not be replaced. Please add any relevant lists and maintainers to the CCs when replying to this mail. Thanks, Mark
diff --git a/sound/soc/fsl/fsl_xcvr.c b/sound/soc/fsl/fsl_xcvr.c index 77f8e2394bf9..f0fb33d719c2 100644 --- a/sound/soc/fsl/fsl_xcvr.c +++ b/sound/soc/fsl/fsl_xcvr.c @@ -358,7 +358,7 @@ static int fsl_xcvr_en_aud_pll(struct fsl_xcvr *xcvr, u32 freq) struct device *dev = &xcvr->pdev->dev; int ret; - freq = xcvr->soc_data->spdif_only ? freq / 10 : freq; + freq = xcvr->soc_data->spdif_only ? freq / 5 : freq; clk_disable_unprepare(xcvr->phy_clk); ret = clk_set_rate(xcvr->phy_clk, freq); if (ret < 0) { @@ -409,7 +409,7 @@ static int fsl_xcvr_prepare(struct snd_pcm_substream *substream, bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK; u32 m_ctl = 0, v_ctl = 0; u32 r = substream->runtime->rate, ch = substream->runtime->channels; - u32 fout = 32 * r * ch * 10 * 2; + u32 fout = 32 * r * ch * 10; int ret = 0; switch (xcvr->mode) {