Message ID | 1700637042-11104-5-git-send-email-quic_cang@quicinc.com |
---|---|
State | New |
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Bottomley" <jejb@linux.ibm.com>, linux-arm-msm@vger.kernel.org (open list:ARM/QUALCOMM SUPPORT), linux-scsi@vger.kernel.org (open list:UNIVERSAL FLASH STORAGE HOST CONTROLLER DRIVER...), linux-kernel@vger.kernel.org (open list) Subject: [PATCH v3 04/11] scsi: ufs: ufs-qcom: Limit negotiated gear to selected PHY gear Date: Tue, 21 Nov 2023 23:10:35 -0800 Message-Id: <1700637042-11104-5-git-send-email-quic_cang@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1700637042-11104-1-git-send-email-quic_cang@quicinc.com> References: <1700637042-11104-1-git-send-email-quic_cang@quicinc.com> X-QCInternal: smtphost X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: PVg95SGpqZAOrBj-K17GVeoupE8iGtK- X-Proofpoint-GUID: PVg95SGpqZAOrBj-K17GVeoupE8iGtK- X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.987,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-11-22_04,2023-11-21_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 mlxscore=0 phishscore=0 bulkscore=0 impostorscore=0 priorityscore=1501 suspectscore=0 lowpriorityscore=0 adultscore=0 spamscore=0 mlxlogscore=999 malwarescore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2311060000 definitions=main-2311220050 X-Spam-Status: No, score=-0.9 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on agentk.vger.email Precedence: bulk List-ID: <linux-kernel.vger.kernel.org> X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (agentk.vger.email [0.0.0.0]); Tue, 21 Nov 2023 23:16:16 -0800 (PST) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1783247606139021800 X-GMAIL-MSGID: 1783247606139021800 |
Series |
Enable HS-G5 support on SM8550
|
|
Commit Message
Can Guo
Nov. 22, 2023, 7:10 a.m. UTC
In the dual init scenario, the initial PHY gear is set to HS-G2, and the
first Power Mode Change (PMC) is meant to find the best matching PHY gear
for the 2nd init. However, for the first PMC, if the negotiated gear (say
HS-G4) is higher than the initial PHY gear, we cannot go ahead let PMC to
the negotiated gear happen, because the programmed UFS PHY settings may not
support the negotiated gear. Fix it by overwriting the negotiated gear with
the PHY gear.
Signed-off-by: Can Guo <quic_cang@quicinc.com>
---
drivers/ufs/host/ufs-qcom.c | 7 ++++++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/drivers/ufs/host/ufs-qcom.c b/drivers/ufs/host/ufs-qcom.c index cc0eb37..d4edf58 100644 --- a/drivers/ufs/host/ufs-qcom.c +++ b/drivers/ufs/host/ufs-qcom.c @@ -920,8 +920,13 @@ static int ufs_qcom_pwr_change_notify(struct ufs_hba *hba, * because, the PHY gear settings are backwards compatible and we only need to * change the PHY gear settings while scaling to higher gears. */ - if (dev_req_params->gear_tx > host->phy_gear) + if (dev_req_params->gear_tx > host->phy_gear) { + u32 old_phy_gear = host->phy_gear; + host->phy_gear = dev_req_params->gear_tx; + dev_req_params->gear_tx = old_phy_gear; + dev_req_params->gear_rx = old_phy_gear; + } /* enable the device ref clock before changing to HS mode */ if (!ufshcd_is_hs_mode(&hba->pwr_info) &&