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From: Mrinmay Sarkar <quic_msarkar@quicinc.com>
To: agross@kernel.org, andersson@kernel.org,
krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org,
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Subject: [PATCH v2 3/3] arm64: dts: qcom: sa8775p: Mark PCIe controller as
cache coherent
Date: Sat, 11 Nov 2023 09:24:35 +0530
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| Series |
arm64: qcom: sa8775p: add cache coherency support for SA8775P
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Commit Message
Mrinmay Sarkar
Nov. 11, 2023, 3:54 a.m. UTC
The PCIe controller on SA8775P supports cache coherency, hence add the
"dma-coherent" property to mark it as such.
Signed-off-by: Mrinmay Sarkar <quic_msarkar@quicinc.com>
---
arch/arm64/boot/dts/qcom/sa8775p.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi index 7eab458..ab01efe 100644 --- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi +++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi @@ -3620,6 +3620,7 @@ <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_0 0>; interconnect-names = "pcie-mem", "cpu-pcie"; + dma-coherent; iommus = <&pcie_smmu 0x0000 0x7f>; resets = <&gcc GCC_PCIE_0_BCR>; reset-names = "core";