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From: Mrinmay Sarkar <quic_msarkar@quicinc.com>
To: agross@kernel.org, andersson@kernel.org,
krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org,
konrad.dybcio@linaro.org, mani@kernel.org, robh+dt@kernel.org
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Subject: [PATCH v1 3/3] arm64: dts: qcom: sa8775p: Mark PCIe controller as
cache coherent
Date: Tue, 31 Oct 2023 21:16:26 +0530
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| Series |
arm64: qcom: sa8775p: add cache coherency support for SA8775P
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Commit Message
Mrinmay Sarkar
Oct. 31, 2023, 3:46 p.m. UTC
The PCIe controller on SA8775P supports cache coherency, hence add the
"dma-coherent" property to mark it as such.
Signed-off-by: Mrinmay Sarkar <quic_msarkar@quicinc.com>
---
arch/arm64/boot/dts/qcom/sa8775p.dtsi | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi index 7eab458..7df941d 100644 --- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi +++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi @@ -3620,6 +3620,8 @@ <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_0 0>; interconnect-names = "pcie-mem", "cpu-pcie"; + dma-coherent; + iommus = <&pcie_smmu 0x0000 0x7f>; resets = <&gcc GCC_PCIE_0_BCR>; reset-names = "core";