Message ID | 1692120000-46900-4-git-send-email-lizhi.hou@amd.com |
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State | New |
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Tue, 15 Aug 2023 12:20:10 -0500 From: Lizhi Hou <lizhi.hou@amd.com> To: <linux-pci@vger.kernel.org>, <devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>, <robh@kernel.org> CC: Lizhi Hou <lizhi.hou@amd.com>, <max.zhen@amd.com>, <sonal.santan@amd.com>, <stefano.stabellini@xilinx.com> Subject: [PATCH V13 3/5] PCI: Add quirks to generate device tree node for Xilinx Alveo U50 Date: Tue, 15 Aug 2023 10:19:58 -0700 Message-ID: <1692120000-46900-4-git-send-email-lizhi.hou@amd.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1692120000-46900-1-git-send-email-lizhi.hou@amd.com> References: <1692120000-46900-1-git-send-email-lizhi.hou@amd.com> MIME-Version: 1.0 Content-Type: text/plain X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SN1PEPF0002636B:EE_|PH7PR12MB9175:EE_ X-MS-Office365-Filtering-Correlation-Id: 476571ec-7c26-4d47-9180-08db9db3e221 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: sLIBME/NEls+iDFXA95ZiPbe82eXoojPTYUu4fruOjtnBhgnpqoYRsr2hQ9aPSMRcMoDlqzbXqflVOmSWT7OZYEtzkxkVoqJszzd1uJSGiFGFP7+18tYdbwroq12QshIoL8kAlM8Q8Ya7/pc8fqHvY7Ub9HCUHsZCecosF8kqoA9Zqvh57be0N1H02Yo5T5BsvrSD0lwKaO6Er60KOUOYrpCES6YiElR3g//33VGoKgvVuHobtVU1kSI187sc7YKzwrX6paXaz5GMED+32aRFR4dEqEZquowFwQAJeO4uXEH8pXwIHQI52lYIBE3jXycCeZR/UwMEw2ddYDy8pg4fMbXUoyAShrqU0ttSE7hGV4EhgN3uNaeEi3QtygbkCKmnbhlMOknGgtwtQl7MIpEJWz4tNyz0IGIXWon/2na6Q86TcOhmY0W9VJWgRUYh8xSrmfSHZWCOYkfnuMWyuD8lOgvaPoWqtrmJj4PyoevANVZYsBWKd6/h68JowBrKfc3XgIBe9tQJaAXuGvJ3kDLJrFw2YYDp1dUySJBU7tthi5VMfWpywETtRdRiobwMx+LDlQp3uE+Z+nZEgB7b9bGf1Sl3z6heGJwxJCirwT6FBqGyjPsF07CCeZK4rXhS7W8NATblNL0fZ9DCPCI2HMJ8RlTj68wgRKULP2gHrMVvh/zS5C30TQyicnYL7fBDzH+swaG6HYAJcFt/tbt9Lc9/oCVWliNeKa1S4tOMhwbJOn+7aTXohG1wIyy5WyYQfbdFAIOBzADCiXRAihttvWWeg== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230031)(4636009)(39860400002)(376002)(346002)(396003)(136003)(1800799009)(186009)(82310400011)(451199024)(46966006)(40470700004)(36840700001)(110136005)(2616005)(26005)(41300700001)(2906002)(54906003)(356005)(6666004)(40460700003)(426003)(336012)(8936002)(82740400003)(4326008)(8676002)(40480700001)(70586007)(36860700001)(316002)(70206006)(86362001)(36756003)(478600001)(81166007)(44832011)(47076005)(5660300002)(36900700001);DIR:OUT;SFP:1101; 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Commit Message
Lizhi Hou
Aug. 15, 2023, 5:19 p.m. UTC
The Xilinx Alveo U50 PCI card exposes multiple hardware peripherals on its PCI BAR. The card firmware provides a flattened device tree to describe the hardware peripherals on its BARs. This allows U50 driver to load the flattened device tree and generate the device tree node for hardware peripherals underneath. To generate device tree node for U50 card, add PCI quirks to call of_pci_make_dev_node() for U50. Acked-by: Bjorn Helgaas <bhelgaas@google.com> Signed-off-by: Lizhi Hou <lizhi.hou@amd.com> --- drivers/pci/quirks.c | 11 +++++++++++ 1 file changed, 11 insertions(+)
diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c index 321156ca273d..6c0e7b6bbdd1 100644 --- a/drivers/pci/quirks.c +++ b/drivers/pci/quirks.c @@ -6138,3 +6138,14 @@ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9a2d, dpc_log_size); DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9a2f, dpc_log_size); DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9a31, dpc_log_size); #endif + +/* + * For a PCI device with multiple downstream devices, its driver may use + * a flattened device tree to describe the downstream devices. + * To overlay the flattened device tree, the PCI device and all its ancestor + * devices need to have device tree nodes on system base device tree. Thus, + * before driver probing, it might need to add a device tree node as the final + * fixup. + */ +DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_XILINX, 0x5020, of_pci_make_dev_node); +DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_XILINX, 0x5021, of_pci_make_dev_node);