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[2620:137:e000::1:20]) by mx.google.com with ESMTP id bh12-20020a170906a0cc00b0099ca9258139si6764730ejb.569.2023.08.08.10.36.29; Tue, 08 Aug 2023 10:36:54 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=nxp.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230417AbjHHRXn (ORCPT + 99 others); Tue, 8 Aug 2023 13:23:43 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42262 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234483AbjHHRXQ (ORCPT ); Tue, 8 Aug 2023 13:23:16 -0400 Received: from inva021.nxp.com (inva021.nxp.com [92.121.34.21]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4890B1E5A4; Tue, 8 Aug 2023 09:09:42 -0700 (PDT) Received: from inva021.nxp.com (localhost [127.0.0.1]) by inva021.eu-rdc02.nxp.com (Postfix) with ESMTP id 28FE62011CA; Tue, 8 Aug 2023 08:08:55 +0200 (CEST) Received: from aprdc01srsp001v.ap-rdc01.nxp.com (aprdc01srsp001v.ap-rdc01.nxp.com [165.114.16.16]) by inva021.eu-rdc02.nxp.com (Postfix) with ESMTP id E27E62011BA; Tue, 8 Aug 2023 08:08:54 +0200 (CEST) Received: from localhost.localdomain (shlinux2.ap.freescale.net [10.192.224.44]) by aprdc01srsp001v.ap-rdc01.nxp.com (Postfix) with ESMTP id 45A48181D0E2; Tue, 8 Aug 2023 14:08:53 +0800 (+08) From: Richard Zhu To: frank.li@nxp.com, l.stach@pengutronix.de, shawnguo@kernel.org, lpieralisi@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org Cc: hongxing.zhu@nxp.com, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, kernel@pengutronix.de, linux-imx@nxp.com Subject: [PATCH v3 1/9] dt-bindings: PCI: fsl,imx6q: Add i.MX6Q and i.MX6QP PCIe EP compatibles Date: Tue, 8 Aug 2023 13:34:10 +0800 Message-Id: <1691472858-9383-2-git-send-email-hongxing.zhu@nxp.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1691472858-9383-1-git-send-email-hongxing.zhu@nxp.com> References: <1691472858-9383-1-git-send-email-hongxing.zhu@nxp.com> X-Virus-Scanned: ClamAV using ClamSMTP X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_BLOCKED,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1773683306172608731 X-GMAIL-MSGID: 1773683306172608731 Add i.MX6Q and i.MX6QP PCIe EP compatibles. - Make the interrupts property optional, since i.MX6Q/i.MX6QP PCIe don't have DMA capability. - To pass the schema check, specify the clocks property refer to the different platforms. Signed-off-by: Richard Zhu Reviewed-by: Krzysztof Kozlowski --- .../bindings/pci/fsl,imx6q-pcie-ep.yaml | 31 ++++++++++++++++--- 1 file changed, 27 insertions(+), 4 deletions(-) diff --git a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie-ep.yaml b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie-ep.yaml index ee155ed5f181..9b881777c801 100644 --- a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie-ep.yaml +++ b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie-ep.yaml @@ -19,6 +19,8 @@ description: |+ properties: compatible: enum: + - fsl,imx6q-pcie-ep + - fsl,imx6qp-pcie-ep - fsl,imx8mm-pcie-ep - fsl,imx8mq-pcie-ep - fsl,imx8mp-pcie-ep @@ -46,7 +48,7 @@ properties: interrupts: items: - - description: builtin eDMA interrupter. + - description: builtin eDMA interrupter (optional). interrupt-names: items: @@ -56,8 +58,6 @@ required: - compatible - reg - reg-names - - interrupts - - interrupt-names allOf: - $ref: /schemas/pci/snps,dw-pcie-ep.yaml# @@ -77,7 +77,30 @@ allOf: - const: pcie_bus - const: pcie_phy - const: pcie_aux - else: + + - if: + properties: + compatible: + enum: + - fsl,imx6q-pcie-ep + - fsl,imx6qp-pcie-ep + then: + properties: + clocks: + maxItems: 3 + clock-names: + items: + - const: pcie + - const: pcie_bus + - const: pcie_phy + + - if: + properties: + compatible: + enum: + - fsl,imx8mm-pcie-ep + - fsl,imx8mp-pcie-ep + then: properties: clocks: maxItems: 3