diff mbox series

[v1,5/6] arm64: dts: qcom: sa8775p: Add pcie0 and pcie1 nodes

Message ID 1688545032-17748-6-git-send-email-quic_msarkar@quicinc.com
State New
Headers
Series arm64: qcom: sa8775p: add support for PCIe |

Commit Message

Mrinmay Sarkar July 5, 2023, 8:17 a.m. UTC 
  Add pcie dtsi nodes for two controllers found on sa8775p platform.

Signed-off-by: Mrinmay Sarkar <quic_msarkar@quicinc.com>
---
 arch/arm64/boot/dts/qcom/sa8775p.dtsi | 201 +++++++++++++++++++++++++-
 1 file changed, 199 insertions(+), 2 deletions(-)

Comments

Manivannan Sadhasivam July 5, 2023, 8:36 a.m. UTC | #1 
On Wed, Jul 05, 2023 at 01:47:10PM +0530, Mrinmay Sarkar wrote:
> Add pcie dtsi nodes for two controllers found on sa8775p platform.
> 
> Signed-off-by: Mrinmay Sarkar <quic_msarkar@quicinc.com>
> ---
>  arch/arm64/boot/dts/qcom/sa8775p.dtsi | 201 +++++++++++++++++++++++++-
>  1 file changed, 199 insertions(+), 2 deletions(-)
> 
> diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
> index b130136acffe..88749cbaea8b 100644
> --- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
> @@ -481,8 +481,8 @@ gcc: clock-controller@100000 {
>  				 <0>,
>  				 <0>,
>  				 <0>,
> -				 <0>,
> -				 <0>,
> +				 <&pcie0_phy>,
> +				 <&pcie1_phy>,
>  				 <0>,
>  				 <0>,
>  				 <0>;
> @@ -2315,4 +2315,201 @@ arch_timer: timer {
>  			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
>  			     <GIC_PPI 12 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
>  	};
> +
> +	pcie0: pci@1c00000{
> +		device_type = "pci";
> +		compatible = "qcom,pcie-sa8775p";
> +		reg = <0x0 0x01c00000 0x0 0x3000>,
> +		      <0x0 0x40000000 0x0 0xf20>,
> +		      <0x0 0x40000f20 0x0 0xa8>,
> +		      <0x0 0x40001000 0x0 0x4000>,
> +		      <0x0 0x40100000 0x0 0x100000>,
> +		      <0x0 0x01c03000 0x0 0x1000>;
> +		reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi";
> +
> +		#address-cells = <3>;
> +		#size-cells = <2>;
> +		ranges = <0x01000000 0x0 0x40200000 0x0 0x40200000 0x0 0x100000>,

<0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>

> +			<0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>;
> +		bus-range = <0x00 0xff>;
> +

Add "dma-coherent" property as the PCIe controller supports cache coherency.

> +		linux,pci-domain = <0>;
> +		num-lanes = <2>;
> +
> +		interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>;
> +		interrupt-names = "msi";

Are you sure that there is only 1 MSI supported on this platform?

> +		#interrupt-cells = <1>;
> +		interrupt-map-mask = <0 0 0 0x7>;
> +		interrupt-map = <0 0 0 1 &intc GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>,
> +			<0 0 0 2 &intc GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>,
> +			<0 0 0 3 &intc GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>,
> +			<0 0 0 4 &intc GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH>;

Align the values.

> +
> +		clocks = <&gcc GCC_PCIE_0_AUX_CLK>,
> +			<&gcc GCC_PCIE_0_CFG_AHB_CLK>,
> +			<&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
> +			<&gcc GCC_PCIE_0_SLV_AXI_CLK>,
> +			<&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>;
> +

Same as above.

> +		clock-names = "aux",
> +				"cfg",
> +				"bus_master",
> +				"bus_slave",
> +				"slave_q2a";

Same as above.

> +
> +		assigned-clocks = <&gcc GCC_PCIE_0_AUX_CLK>;
> +		assigned-clock-rates = <19200000>;
> +
> +		interconnects = <&pcie_anoc MASTER_PCIE_0 0 &mc_virt SLAVE_EBI1 0>;

Why no cpu-pcie path?

> +		interconnect-names = "pcie-mem";
> +
> +		resets = <&gcc GCC_PCIE_0_BCR>;
> +		reset-names = "pci";
> +		power-domains = <&gcc PCIE_0_GDSC>;
> +
> +		phys = <&pcie0_phy>;
> +		phy-names = "pciephy";
> +
> +		iommus = <&pcie_smmu 0x0000 0x1>;

This property is not needed.

> +		iommu-map = <0x0 &pcie_smmu 0x0000 0x1>,
> +			<0x100 &pcie_smmu 0x0001 0x1>;
> +
> +		perst-gpios = <&tlmm 2 1>;
> +		wake-gpios = <&tlmm 0 0>;
> +
> +		pinctrl-names = "default";
> +		pinctrl-0 = <&pcie0_default_state>;

Move the pinctrl and gpio properties to board dts.

All of the above comment applies to other PCIe node below.

- Mani

> +
> +		status = "disabled";
> +	};
> +
> +	pcie0_phy: phy@1c04000 {
> +		compatible = "qcom,sa8775p-qmp-gen4x2-pcie-phy";
> +		reg = <0x0 0x1c04000 0x0 0x2000>;
> +
> +		clocks = <&gcc GCC_PCIE_0_AUX_CLK>,
> +			 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
> +			 <&gcc GCC_PCIE_CLKREF_EN>,
> +			 <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>,
> +			 <&gcc GCC_PCIE_0_PHY_AUX_CLK>,
> +			 <&gcc GCC_PCIE_0_PIPE_CLK>,
> +			 <&gcc GCC_PCIE_0_PIPEDIV2_CLK>;
> +
> +		clock-names = "aux", "cfg_ahb", "ref", "rchng", "phy_aux",
> +						"pipe", "pipediv2";
> +
> +		assigned-clocks = <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>;
> +		assigned-clock-rates = <100000000>;
> +
> +		power-domains = <&gcc PCIE_0_GDSC>;
> +
> +		resets = <&gcc GCC_PCIE_0_PHY_BCR>;
> +		reset-names = "phy";
> +
> +		#clock-cells = <0>;
> +		clock-output-names = "pcie_0_pipe_clk";
> +
> +		#phy-cells = <0>;
> +
> +		status = "disabled";
> +	};
> +
> +	pcie1: pci@1c10000{
> +		device_type = "pci";
> +		compatible = "qcom,pcie-sa8775p";
> +		reg = <0x0 0x01c10000 0x0 0x3000>,
> +		      <0x0 0x60000000 0x0 0xf20>,
> +		      <0x0 0x60000f20 0x0 0xa8>,
> +		      <0x0 0x60001000 0x0 0x4000>,
> +		      <0x0 0x60100000 0x0 0x100000>,
> +		      <0x0 0x01c13000 0x0 0x1000>;
> +		reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi";
> +
> +		#address-cells = <3>;
> +		#size-cells = <2>;
> +		ranges = <0x01000000 0x0 0x60200000 0x0 0x60200000 0x0 0x100000>,
> +			<0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x1fd00000>;
> +		bus-range = <0x00 0xff>;
> +
> +		linux,pci-domain = <1>;
> +		num-lanes = <4>;
> +
> +		interrupts = <GIC_SPI 519 IRQ_TYPE_LEVEL_HIGH>;
> +		interrupt-names = "msi";
> +		#interrupt-cells = <1>;
> +		interrupt-map-mask = <0 0 0 0x7>;
> +		interrupt-map = <0 0 0 1 &intc GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
> +				<0 0 0 2 &intc GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
> +				<0 0 0 3 &intc GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
> +				<0 0 0 4 &intc GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
> +
> +		clocks = <&gcc GCC_PCIE_1_AUX_CLK>,
> +			<&gcc GCC_PCIE_1_CFG_AHB_CLK>,
> +			<&gcc GCC_PCIE_1_MSTR_AXI_CLK>,
> +			<&gcc GCC_PCIE_1_SLV_AXI_CLK>,
> +			<&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>;
> +
> +		clock-names = "aux",
> +				"cfg",
> +				"bus_master",
> +				"bus_slave",
> +				"slave_q2a";
> +
> +		assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>;
> +		assigned-clock-rates = <19200000>;
> +
> +		interconnects = <&pcie_anoc MASTER_PCIE_1 0 &mc_virt SLAVE_EBI1 0>;
> +		interconnect-names = "pcie-mem";
> +
> +		resets = <&gcc GCC_PCIE_1_BCR>;
> +		reset-names = "pci";
> +		power-domains = <&gcc PCIE_1_GDSC>;
> +
> +		phys = <&pcie1_phy>;
> +		phy-names = "pciephy";
> +
> +		iommus = <&pcie_smmu 0x0080 0x1>;
> +		iommu-map = <0x0 &pcie_smmu 0x0080 0x1>,
> +			<0x100 &pcie_smmu 0x0081 0x1>;
> +
> +		perst-gpios = <&tlmm 4 1>;
> +		wake-gpios = <&tlmm 5 0>;
> +
> +		pinctrl-names = "default";
> +		pinctrl-0 = <&pcie1_default_state>;
> +
> +		status = "disabled";
> +	};
> +
> +	pcie1_phy: phy@1c14000 {
> +		compatible = "qcom,sa8775p-qmp-gen4x4-pcie-phy";
> +		reg = <0x0 0x1c14000 0x0 0x4000>;
> +
> +		clocks = <&gcc GCC_PCIE_1_AUX_CLK>,
> +			 <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
> +			 <&gcc GCC_PCIE_CLKREF_EN>,
> +			 <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>,
> +			 <&gcc GCC_PCIE_1_PHY_AUX_CLK>,
> +			 <&gcc GCC_PCIE_1_PIPE_CLK>,
> +			 <&gcc GCC_PCIE_1_PIPEDIV2_CLK>;
> +
> +		clock-names = "aux", "cfg_ahb", "ref", "rchng", "phy_aux",
> +						"pipe", "pipediv2";
> +
> +		assigned-clocks = <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>;
> +		assigned-clock-rates = <100000000>;
> +
> +		power-domains = <&gcc PCIE_1_GDSC>;
> +
> +		resets = <&gcc GCC_PCIE_1_PHY_BCR>;
> +		reset-names = "phy";
> +
> +		#clock-cells = <0>;
> +		clock-output-names = "pcie_1_pipe_clk";
> +
> +		#phy-cells = <0>;
> +
> +		status = "disabled";
> +
> +	};
>  };
> -- 
> 2.39.2
>
Krzysztof Kozlowski July 6, 2023, 6:38 a.m. UTC | #2 
On 05/07/2023 10:17, Mrinmay Sarkar wrote:
> Add pcie dtsi nodes for two controllers found on sa8775p platform.
> 
> Signed-off-by: Mrinmay Sarkar <quic_msarkar@quicinc.com>
> ---
>  arch/arm64/boot/dts/qcom/sa8775p.dtsi | 201 +++++++++++++++++++++++++-
>  1 file changed, 199 insertions(+), 2 deletions(-)
> 
> diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
> index b130136acffe..88749cbaea8b 100644
> --- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
> @@ -481,8 +481,8 @@ gcc: clock-controller@100000 {
>  				 <0>,
>  				 <0>,
>  				 <0>,
> -				 <0>,
> -				 <0>,
> +				 <&pcie0_phy>,
> +				 <&pcie1_phy>,
>  				 <0>,
>  				 <0>,
>  				 <0>;
> @@ -2315,4 +2315,201 @@ arch_timer: timer {
>  			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
>  			     <GIC_PPI 12 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
>  	};
> +
> +	pcie0: pci@1c00000{
> +		device_type = "pci";
> +		compatible = "qcom,pcie-sa8775p";
> +		reg = <0x0 0x01c00000 0x0 0x3000>,
> +		      <0x0 0x40000000 0x0 0xf20>,
> +		      <0x0 0x40000f20 0x0 0xa8>,
> +		      <0x0 0x40001000 0x0 0x4000>,
> +		      <0x0 0x40100000 0x0 0x100000>,
> +		      <0x0 0x01c03000 0x0 0x1000>;
> +		reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi";
> +
> +		#address-cells = <3>;
> +		#size-cells = <2>;
> +		ranges = <0x01000000 0x0 0x40200000 0x0 0x40200000 0x0 0x100000>,
> +			<0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>;
> +		bus-range = <0x00 0xff>;
> +
> +		linux,pci-domain = <0>;
> +		num-lanes = <2>;
> +
> +		interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>;
> +		interrupt-names = "msi";
> +		#interrupt-cells = <1>;
> +		interrupt-map-mask = <0 0 0 0x7>;
> +		interrupt-map = <0 0 0 1 &intc GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>,
> +			<0 0 0 2 &intc GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>,
> +			<0 0 0 3 &intc GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>,
> +			<0 0 0 4 &intc GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH>;
> +
> +		clocks = <&gcc GCC_PCIE_0_AUX_CLK>,
> +			<&gcc GCC_PCIE_0_CFG_AHB_CLK>,
> +			<&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
> +			<&gcc GCC_PCIE_0_SLV_AXI_CLK>,
> +			<&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>;
> +
> +		clock-names = "aux",
> +				"cfg",
> +				"bus_master",
> +				"bus_slave",
> +				"slave_q2a";
> +
> +		assigned-clocks = <&gcc GCC_PCIE_0_AUX_CLK>;
> +		assigned-clock-rates = <19200000>;
> +
> +		interconnects = <&pcie_anoc MASTER_PCIE_0 0 &mc_virt SLAVE_EBI1 0>;
> +		interconnect-names = "pcie-mem";
> +
> +		resets = <&gcc GCC_PCIE_0_BCR>;
> +		reset-names = "pci";
> +		power-domains = <&gcc PCIE_0_GDSC>;
> +
> +		phys = <&pcie0_phy>;
> +		phy-names = "pciephy";
> +
> +		iommus = <&pcie_smmu 0x0000 0x1>;
> +		iommu-map = <0x0 &pcie_smmu 0x0000 0x1>,
> +			<0x100 &pcie_smmu 0x0001 0x1>;
> +
> +		perst-gpios = <&tlmm 2 1>;
> +		wake-gpios = <&tlmm 0 0>;
> +
> +		pinctrl-names = "default";
> +		pinctrl-0 = <&pcie0_default_state>;
> +
> +		status = "disabled";
> +	};
> +
> +	pcie0_phy: phy@1c04000 {
> +		compatible = "qcom,sa8775p-qmp-gen4x2-pcie-phy";
> +		reg = <0x0 0x1c04000 0x0 0x2000>;
> +
> +		clocks = <&gcc GCC_PCIE_0_AUX_CLK>,
> +			 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
> +			 <&gcc GCC_PCIE_CLKREF_EN>,
> +			 <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>,
> +			 <&gcc GCC_PCIE_0_PHY_AUX_CLK>,
> +			 <&gcc GCC_PCIE_0_PIPE_CLK>,
> +			 <&gcc GCC_PCIE_0_PIPEDIV2_CLK>;
> +
> +		clock-names = "aux", "cfg_ahb", "ref", "rchng", "phy_aux",
> +						"pipe", "pipediv2";
> +
> +		assigned-clocks = <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>;
> +		assigned-clock-rates = <100000000>;
> +
> +		power-domains = <&gcc PCIE_0_GDSC>;
> +
> +		resets = <&gcc GCC_PCIE_0_PHY_BCR>;
> +		reset-names = "phy";
> +
> +		#clock-cells = <0>;
> +		clock-output-names = "pcie_0_pipe_clk";
> +
> +		#phy-cells = <0>;
> +
> +		status = "disabled";
> +	};
> +
> +	pcie1: pci@1c10000{
> +		device_type = "pci";

compatible is always first property, then reg, then reg-names, then
ranges. Always.

> +		compatible = "qcom,pcie-sa8775p";
> +		reg = <0x0 0x01c10000 0x0 0x3000>,
> +		      <0x0 0x60000000 0x0 0xf20>,
> +		      <0x0 0x60000f20 0x0 0xa8>,
> +		      <0x0 0x60001000 0x0 0x4000>,
> +		      <0x0 0x60100000 0x0 0x100000>,
> +		      <0x0 0x01c13000 0x0 0x1000>;
> +		reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi";
> +
> +		#address-cells = <3>;
> +		#size-cells = <2>;
> +		ranges = <0x01000000 0x0 0x60200000 0x0 0x60200000 0x0 0x100000>,
> +			<0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x1fd00000>;
> +		bus-range = <0x00 0xff>;
> +
> +		linux,pci-domain = <1>;
> +		num-lanes = <4>;
> +
> +		interrupts = <GIC_SPI 519 IRQ_TYPE_LEVEL_HIGH>;
> +		interrupt-names = "msi";
> +		#interrupt-cells = <1>;
> +		interrupt-map-mask = <0 0 0 0x7>;
> +		interrupt-map = <0 0 0 1 &intc GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
> +				<0 0 0 2 &intc GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
> +				<0 0 0 3 &intc GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
> +				<0 0 0 4 &intc GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
> +
> +		clocks = <&gcc GCC_PCIE_1_AUX_CLK>,
> +			<&gcc GCC_PCIE_1_CFG_AHB_CLK>,
> +			<&gcc GCC_PCIE_1_MSTR_AXI_CLK>,
> +			<&gcc GCC_PCIE_1_SLV_AXI_CLK>,
> +			<&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>;
> +
> +		clock-names = "aux",
> +				"cfg",
> +				"bus_master",
> +				"bus_slave",
> +				"slave_q2a";
> +
> +		assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>;
> +		assigned-clock-rates = <19200000>;
> +
> +		interconnects = <&pcie_anoc MASTER_PCIE_1 0 &mc_virt SLAVE_EBI1 0>;
> +		interconnect-names = "pcie-mem";
> +
> +		resets = <&gcc GCC_PCIE_1_BCR>;
> +		reset-names = "pci";
> +		power-domains = <&gcc PCIE_1_GDSC>;
> +
> +		phys = <&pcie1_phy>;
> +		phy-names = "pciephy";
> +
> +		iommus = <&pcie_smmu 0x0080 0x1>;
> +		iommu-map = <0x0 &pcie_smmu 0x0080 0x1>,
> +			<0x100 &pcie_smmu 0x0081 0x1>;
> +
> +		perst-gpios = <&tlmm 4 1>;
> +		wake-gpios = <&tlmm 5 0>;

Use proper defines.

> +
> +		pinctrl-names = "default";
> +		pinctrl-0 = <&pcie1_default_state>;
> +
> +		status = "disabled";
> +	};
> +
> +	pcie1_phy: phy@1c14000 {
> +		compatible = "qcom,sa8775p-qmp-gen4x4-pcie-phy";
> +		reg = <0x0 0x1c14000 0x0 0x4000>;
> +
> +		clocks = <&gcc GCC_PCIE_1_AUX_CLK>,
> +			 <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
> +			 <&gcc GCC_PCIE_CLKREF_EN>,
> +			 <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>,
> +			 <&gcc GCC_PCIE_1_PHY_AUX_CLK>,
> +			 <&gcc GCC_PCIE_1_PIPE_CLK>,
> +			 <&gcc GCC_PCIE_1_PIPEDIV2_CLK>;
> +
> +		clock-names = "aux", "cfg_ahb", "ref", "rchng", "phy_aux",
> +						"pipe", "pipediv2";
> +
> +		assigned-clocks = <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>;
> +		assigned-clock-rates = <100000000>;
> +
> +		power-domains = <&gcc PCIE_1_GDSC>;
> +
> +		resets = <&gcc GCC_PCIE_1_PHY_BCR>;
> +		reset-names = "phy";
> +
> +		#clock-cells = <0>;
> +		clock-output-names = "pcie_1_pipe_clk";
> +
> +		#phy-cells = <0>;
> +
> +		status = "disabled";
> +

No stray blank lines.

> +	};
>  };

Best regards,
Krzysztof
Konrad Dybcio July 6, 2023, 10:01 a.m. UTC | #3 
On 5.07.2023 10:17, Mrinmay Sarkar wrote:
> Add pcie dtsi nodes for two controllers found on sa8775p platform.
> 
> Signed-off-by: Mrinmay Sarkar <quic_msarkar@quicinc.com>
> ---[...]

> +	pcie1_phy: phy@1c14000 {
> +		compatible = "qcom,sa8775p-qmp-gen4x4-pcie-phy";
> +		reg = <0x0 0x1c14000 0x0 0x4000>;
> +
> +		clocks = <&gcc GCC_PCIE_1_AUX_CLK>,
> +			 <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
> +			 <&gcc GCC_PCIE_CLKREF_EN>,
> +			 <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>,
> +			 <&gcc GCC_PCIE_1_PHY_AUX_CLK>,
> +			 <&gcc GCC_PCIE_1_PIPE_CLK>,
> +			 <&gcc GCC_PCIE_1_PIPEDIV2_CLK>;
> +
> +		clock-names = "aux", "cfg_ahb", "ref", "rchng", "phy_aux",
> +						"pipe", "pipediv2";
> +
> +		assigned-clocks = <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>;
> +		assigned-clock-rates = <100000000>;
> +
> +		power-domains = <&gcc PCIE_1_GDSC>;
Please check if it's the correct power domain. I've heard that the PCIe PHY
may be hooked up to something else but have no way of confirming myself.

Konrad
> +
> +		resets = <&gcc GCC_PCIE_1_PHY_BCR>;
> +		reset-names = "phy";
> +
> +		#clock-cells = <0>;
> +		clock-output-names = "pcie_1_pipe_clk";
> +
> +		#phy-cells = <0>;
> +
> +		status = "disabled";
> +
> +	};
>  };
Manivannan Sadhasivam July 6, 2023, 11:15 a.m. UTC | #4 
On Thu, Jul 06, 2023 at 12:01:37PM +0200, Konrad Dybcio wrote:
> On 5.07.2023 10:17, Mrinmay Sarkar wrote:
> > Add pcie dtsi nodes for two controllers found on sa8775p platform.
> > 
> > Signed-off-by: Mrinmay Sarkar <quic_msarkar@quicinc.com>
> > ---[...]
> 
> > +	pcie1_phy: phy@1c14000 {
> > +		compatible = "qcom,sa8775p-qmp-gen4x4-pcie-phy";
> > +		reg = <0x0 0x1c14000 0x0 0x4000>;
> > +
> > +		clocks = <&gcc GCC_PCIE_1_AUX_CLK>,
> > +			 <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
> > +			 <&gcc GCC_PCIE_CLKREF_EN>,
> > +			 <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>,
> > +			 <&gcc GCC_PCIE_1_PHY_AUX_CLK>,
> > +			 <&gcc GCC_PCIE_1_PIPE_CLK>,
> > +			 <&gcc GCC_PCIE_1_PIPEDIV2_CLK>;
> > +
> > +		clock-names = "aux", "cfg_ahb", "ref", "rchng", "phy_aux",
> > +						"pipe", "pipediv2";
> > +
> > +		assigned-clocks = <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>;
> > +		assigned-clock-rates = <100000000>;
> > +
> > +		power-domains = <&gcc PCIE_1_GDSC>;
> Please check if it's the correct power domain. I've heard that the PCIe PHY
> may be hooked up to something else but have no way of confirming myself.
> 

Right, I missed it during my review. PHYs are powered by MX domain on all the
platforms I have seen so far, so this should be cross checked.

And someone should fix the existing dts.

- Mani

> Konrad
> > +
> > +		resets = <&gcc GCC_PCIE_1_PHY_BCR>;
> > +		reset-names = "phy";
> > +
> > +		#clock-cells = <0>;
> > +		clock-output-names = "pcie_1_pipe_clk";
> > +
> > +		#phy-cells = <0>;
> > +
> > +		status = "disabled";
> > +
> > +	};
> >  };
diff mbox series

Patch

diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
index b130136acffe..88749cbaea8b 100644
--- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi
+++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
@@ -481,8 +481,8 @@  gcc: clock-controller@100000 {
 				 <0>,
 				 <0>,
 				 <0>,
-				 <0>,
-				 <0>,
+				 <&pcie0_phy>,
+				 <&pcie1_phy>,
 				 <0>,
 				 <0>,
 				 <0>;
@@ -2315,4 +2315,201 @@  arch_timer: timer {
 			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
 			     <GIC_PPI 12 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
 	};
+
+	pcie0: pci@1c00000{
+		device_type = "pci";
+		compatible = "qcom,pcie-sa8775p";
+		reg = <0x0 0x01c00000 0x0 0x3000>,
+		      <0x0 0x40000000 0x0 0xf20>,
+		      <0x0 0x40000f20 0x0 0xa8>,
+		      <0x0 0x40001000 0x0 0x4000>,
+		      <0x0 0x40100000 0x0 0x100000>,
+		      <0x0 0x01c03000 0x0 0x1000>;
+		reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi";
+
+		#address-cells = <3>;
+		#size-cells = <2>;
+		ranges = <0x01000000 0x0 0x40200000 0x0 0x40200000 0x0 0x100000>,
+			<0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>;
+		bus-range = <0x00 0xff>;
+
+		linux,pci-domain = <0>;
+		num-lanes = <2>;
+
+		interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-names = "msi";
+		#interrupt-cells = <1>;
+		interrupt-map-mask = <0 0 0 0x7>;
+		interrupt-map = <0 0 0 1 &intc GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>,
+			<0 0 0 2 &intc GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>,
+			<0 0 0 3 &intc GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>,
+			<0 0 0 4 &intc GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH>;
+
+		clocks = <&gcc GCC_PCIE_0_AUX_CLK>,
+			<&gcc GCC_PCIE_0_CFG_AHB_CLK>,
+			<&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
+			<&gcc GCC_PCIE_0_SLV_AXI_CLK>,
+			<&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>;
+
+		clock-names = "aux",
+				"cfg",
+				"bus_master",
+				"bus_slave",
+				"slave_q2a";
+
+		assigned-clocks = <&gcc GCC_PCIE_0_AUX_CLK>;
+		assigned-clock-rates = <19200000>;
+
+		interconnects = <&pcie_anoc MASTER_PCIE_0 0 &mc_virt SLAVE_EBI1 0>;
+		interconnect-names = "pcie-mem";
+
+		resets = <&gcc GCC_PCIE_0_BCR>;
+		reset-names = "pci";
+		power-domains = <&gcc PCIE_0_GDSC>;
+
+		phys = <&pcie0_phy>;
+		phy-names = "pciephy";
+
+		iommus = <&pcie_smmu 0x0000 0x1>;
+		iommu-map = <0x0 &pcie_smmu 0x0000 0x1>,
+			<0x100 &pcie_smmu 0x0001 0x1>;
+
+		perst-gpios = <&tlmm 2 1>;
+		wake-gpios = <&tlmm 0 0>;
+
+		pinctrl-names = "default";
+		pinctrl-0 = <&pcie0_default_state>;
+
+		status = "disabled";
+	};
+
+	pcie0_phy: phy@1c04000 {
+		compatible = "qcom,sa8775p-qmp-gen4x2-pcie-phy";
+		reg = <0x0 0x1c04000 0x0 0x2000>;
+
+		clocks = <&gcc GCC_PCIE_0_AUX_CLK>,
+			 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
+			 <&gcc GCC_PCIE_CLKREF_EN>,
+			 <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>,
+			 <&gcc GCC_PCIE_0_PHY_AUX_CLK>,
+			 <&gcc GCC_PCIE_0_PIPE_CLK>,
+			 <&gcc GCC_PCIE_0_PIPEDIV2_CLK>;
+
+		clock-names = "aux", "cfg_ahb", "ref", "rchng", "phy_aux",
+						"pipe", "pipediv2";
+
+		assigned-clocks = <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>;
+		assigned-clock-rates = <100000000>;
+
+		power-domains = <&gcc PCIE_0_GDSC>;
+
+		resets = <&gcc GCC_PCIE_0_PHY_BCR>;
+		reset-names = "phy";
+
+		#clock-cells = <0>;
+		clock-output-names = "pcie_0_pipe_clk";
+
+		#phy-cells = <0>;
+
+		status = "disabled";
+	};
+
+	pcie1: pci@1c10000{
+		device_type = "pci";
+		compatible = "qcom,pcie-sa8775p";
+		reg = <0x0 0x01c10000 0x0 0x3000>,
+		      <0x0 0x60000000 0x0 0xf20>,
+		      <0x0 0x60000f20 0x0 0xa8>,
+		      <0x0 0x60001000 0x0 0x4000>,
+		      <0x0 0x60100000 0x0 0x100000>,
+		      <0x0 0x01c13000 0x0 0x1000>;
+		reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi";
+
+		#address-cells = <3>;
+		#size-cells = <2>;
+		ranges = <0x01000000 0x0 0x60200000 0x0 0x60200000 0x0 0x100000>,
+			<0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x1fd00000>;
+		bus-range = <0x00 0xff>;
+
+		linux,pci-domain = <1>;
+		num-lanes = <4>;
+
+		interrupts = <GIC_SPI 519 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-names = "msi";
+		#interrupt-cells = <1>;
+		interrupt-map-mask = <0 0 0 0x7>;
+		interrupt-map = <0 0 0 1 &intc GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
+				<0 0 0 2 &intc GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
+				<0 0 0 3 &intc GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
+				<0 0 0 4 &intc GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
+
+		clocks = <&gcc GCC_PCIE_1_AUX_CLK>,
+			<&gcc GCC_PCIE_1_CFG_AHB_CLK>,
+			<&gcc GCC_PCIE_1_MSTR_AXI_CLK>,
+			<&gcc GCC_PCIE_1_SLV_AXI_CLK>,
+			<&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>;
+
+		clock-names = "aux",
+				"cfg",
+				"bus_master",
+				"bus_slave",
+				"slave_q2a";
+
+		assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>;
+		assigned-clock-rates = <19200000>;
+
+		interconnects = <&pcie_anoc MASTER_PCIE_1 0 &mc_virt SLAVE_EBI1 0>;
+		interconnect-names = "pcie-mem";
+
+		resets = <&gcc GCC_PCIE_1_BCR>;
+		reset-names = "pci";
+		power-domains = <&gcc PCIE_1_GDSC>;
+
+		phys = <&pcie1_phy>;
+		phy-names = "pciephy";
+
+		iommus = <&pcie_smmu 0x0080 0x1>;
+		iommu-map = <0x0 &pcie_smmu 0x0080 0x1>,
+			<0x100 &pcie_smmu 0x0081 0x1>;
+
+		perst-gpios = <&tlmm 4 1>;
+		wake-gpios = <&tlmm 5 0>;
+
+		pinctrl-names = "default";
+		pinctrl-0 = <&pcie1_default_state>;
+
+		status = "disabled";
+	};
+
+	pcie1_phy: phy@1c14000 {
+		compatible = "qcom,sa8775p-qmp-gen4x4-pcie-phy";
+		reg = <0x0 0x1c14000 0x0 0x4000>;
+
+		clocks = <&gcc GCC_PCIE_1_AUX_CLK>,
+			 <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
+			 <&gcc GCC_PCIE_CLKREF_EN>,
+			 <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>,
+			 <&gcc GCC_PCIE_1_PHY_AUX_CLK>,
+			 <&gcc GCC_PCIE_1_PIPE_CLK>,
+			 <&gcc GCC_PCIE_1_PIPEDIV2_CLK>;
+
+		clock-names = "aux", "cfg_ahb", "ref", "rchng", "phy_aux",
+						"pipe", "pipediv2";
+
+		assigned-clocks = <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>;
+		assigned-clock-rates = <100000000>;
+
+		power-domains = <&gcc PCIE_1_GDSC>;
+
+		resets = <&gcc GCC_PCIE_1_PHY_BCR>;
+		reset-names = "phy";
+
+		#clock-cells = <0>;
+		clock-output-names = "pcie_1_pipe_clk";
+
+		#phy-cells = <0>;
+
+		status = "disabled";
+
+	};
 };