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Subject: [tip: x86/cleanups] x86/mm: Remove unused current_untag_mask()
Cc: "Borislav Petkov (AMD)" <bp@alien8.de>,
"Kirill A. Shutemov" <kirill.shutemov@linux.intel.com>,
x86@kernel.org, linux-kernel@vger.kernel.org
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[tip:,x86/cleanups] x86/mm: Remove unused current_untag_mask()
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Commit Message
tip-bot2 for Thomas Gleixner
June 16, 2023, 9:02 a.m. UTC
The following commit has been merged into the x86/cleanups branch of tip:
Commit-ID: 013fdeb07a8fd32bbb3412e5f49d60207a78bf08
Gitweb: https://git.kernel.org/tip/013fdeb07a8fd32bbb3412e5f49d60207a78bf08
Author: Borislav Petkov (AMD) <bp@alien8.de>
AuthorDate: Wed, 14 Jun 2023 19:41:48 +02:00
Committer: Borislav Petkov (AMD) <bp@alien8.de>
CommitterDate: Fri, 16 Jun 2023 10:50:16 +02:00
x86/mm: Remove unused current_untag_mask()
e0bddc19ba95 ("x86/mm: Reduce untagged_addr() overhead for systems without LAM")
removed its only usage site so drop it.
Move the tlbstate_untag_mask up in the header and drop the ugly
ifdeffery as the unused declaration should be properly discarded.
Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de>
Acked-by: Kirill A. Shutemov <kirill.shutemov@linux.intel.com>
Link: https://lore.kernel.org/r/20230614174148.5439-1-bp@alien8.de
---
arch/x86/include/asm/tlbflush.h | 11 ++---------
1 file changed, 2 insertions(+), 9 deletions(-)
diff --git a/arch/x86/include/asm/tlbflush.h b/arch/x86/include/asm/tlbflush.h index 75bfaa4..80450e1 100644 --- a/arch/x86/include/asm/tlbflush.h +++ b/arch/x86/include/asm/tlbflush.h @@ -14,6 +14,8 @@ #include <asm/processor-flags.h> #include <asm/pgtable.h> +DECLARE_PER_CPU(u64, tlbstate_untag_mask); + void __flush_tlb_all(void); #define TLB_FLUSH_ALL -1UL @@ -54,15 +56,6 @@ static inline void cr4_clear_bits(unsigned long mask) local_irq_restore(flags); } -#ifdef CONFIG_ADDRESS_MASKING -DECLARE_PER_CPU(u64, tlbstate_untag_mask); - -static inline u64 current_untag_mask(void) -{ - return this_cpu_read(tlbstate_untag_mask); -} -#endif - #ifndef MODULE /* * 6 because 6 should be plenty and struct tlb_state will fit in two cache