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[2620:137:e000::1:20]) by mx.google.com with ESMTP id p3-20020a05620a132300b0074a8ab7b4b2si5588207qkj.142.2023.06.06.01.56.08; Tue, 06 Jun 2023 01:56:22 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=zOFBSXbM; dkim=neutral (no key) header.i=@linutronix.de; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236652AbjFFI1Z (ORCPT + 99 others); Tue, 6 Jun 2023 04:27:25 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53720 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236482AbjFFI0g (ORCPT ); Tue, 6 Jun 2023 04:26:36 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 415F0E62; Tue, 6 Jun 2023 01:26:26 -0700 (PDT) Date: Tue, 06 Jun 2023 08:26:21 -0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1686039981; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=TysD+5asBdNuqSOwatIKtTdmwVtVQRZlGM91vHX3JkI=; b=zOFBSXbMXcxC0dRIyXR1F9ttxRcm7AVnlGHnymjUkBrUnBv4CUq3pGhc6FLlEcJKTTL8xD t/TiPZ2nPYQoAJpO8EKHdL3b5mLzTJPjSyRW6W1HXba9Vh4dNq6togsUE78a+QswdzxMDl s+DW5vgMgDRtgYZbc13GC4YZf+QmuRqqGeCxcB1V8HX6FRDqfvNd6hlFFWqNuvQqTRxh1V +z8fXNTXbB5KKBiAzLIJiO9YW4qk5XCjUHxhgR8ERa/x2XS+i4Gk7amzRcYmYTHrIH0gLg 7PT0dnxspsl+NeHNnc6MLRCzXkAmfB9qxpnn9U4f2Rp8iTKWSTmuUyn8jpEqrg== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1686039981; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=TysD+5asBdNuqSOwatIKtTdmwVtVQRZlGM91vHX3JkI=; b=/9TwFhLQRETWTylT5QUNNZmVowUJjkgTTp1/blBT9GbmLP6CrFSHLTbe+1qAP00Iany6Ju rmeZMMfhCVkSszBA== From: "tip-bot2 for Mark Rutland" Sender: tip-bot2@linutronix.de Reply-to: linux-kernel@vger.kernel.org To: linux-tip-commits@vger.kernel.org Subject: [tip: locking/core] locking/atomic: xtensa: add preprocessor symbols Cc: Mark Rutland , "Peter Zijlstra (Intel)" , Kees Cook , x86@kernel.org, linux-kernel@vger.kernel.org In-Reply-To: <20230605070124.3741859-14-mark.rutland@arm.com> References: <20230605070124.3741859-14-mark.rutland@arm.com> MIME-Version: 1.0 Message-ID: <168603998121.404.11675636591884736472.tip-bot2@tip-bot2> Robot-ID: Robot-Unsubscribe: Contact to get blacklisted from these emails X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED,SPF_HELO_NONE, SPF_PASS,T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1767845752563506132?= X-GMAIL-MSGID: =?utf-8?q?1767942947669220891?= The following commit has been merged into the locking/core branch of tip: Commit-ID: 7c7084f3ba4031a9c2858afed696a577fcfe41d2 Gitweb: https://git.kernel.org/tip/7c7084f3ba4031a9c2858afed696a577fcfe41d2 Author: Mark Rutland AuthorDate: Mon, 05 Jun 2023 08:01:10 +01:00 Committer: Peter Zijlstra CommitterDate: Mon, 05 Jun 2023 09:57:18 +02:00 locking/atomic: xtensa: add preprocessor symbols Some atomics can be implemented in several different ways, e.g. FULL/ACQUIRE/RELEASE ordered atomics can be implemented in terms of RELAXED atomics, and ACQUIRE/RELEASE/RELAXED can be implemented in terms of FULL ordered atomics. Other atomics are optional, and don't exist in some configurations (e.g. not all architectures implement the 128-bit cmpxchg ops). Subsequent patches will require that architectures define a preprocessor symbol for any atomic (or ordering variant) which is optional. This will make the fallback ifdeffery more robust, and simplify future changes. Add the required definitions to arch/xtensa. Signed-off-by: Mark Rutland Signed-off-by: Peter Zijlstra (Intel) Reviewed-by: Kees Cook Link: https://lore.kernel.org/r/20230605070124.3741859-14-mark.rutland@arm.com --- arch/xtensa/include/asm/atomic.h | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/xtensa/include/asm/atomic.h b/arch/xtensa/include/asm/atomic.h index 1d323a8..7308b7f 100644 --- a/arch/xtensa/include/asm/atomic.h +++ b/arch/xtensa/include/asm/atomic.h @@ -245,6 +245,11 @@ static inline int arch_atomic_fetch_##op(int i, atomic_t * v) \ ATOMIC_OPS(add) ATOMIC_OPS(sub) +#define arch_atomic_add_return arch_atomic_add_return +#define arch_atomic_sub_return arch_atomic_sub_return +#define arch_atomic_fetch_add arch_atomic_fetch_add +#define arch_atomic_fetch_sub arch_atomic_fetch_sub + #undef ATOMIC_OPS #define ATOMIC_OPS(op) ATOMIC_OP(op) ATOMIC_FETCH_OP(op) @@ -252,6 +257,10 @@ ATOMIC_OPS(and) ATOMIC_OPS(or) ATOMIC_OPS(xor) +#define arch_atomic_fetch_and arch_atomic_fetch_and +#define arch_atomic_fetch_or arch_atomic_fetch_or +#define arch_atomic_fetch_xor arch_atomic_fetch_xor + #undef ATOMIC_OPS #undef ATOMIC_FETCH_OP #undef ATOMIC_OP_RETURN