diff mbox series

[tip:,x86/mtrr] x86/hyperv: Set MTRR state when running as SEV-SNP Hyper-V guest

Message ID 168597409682.404.2522096676257055244.tip-bot2@tip-bot2
State New
Headers
Series [tip:,x86/mtrr] x86/hyperv: Set MTRR state when running as SEV-SNP Hyper-V guest |

Commit Message

tip-bot2 for Thomas Gleixner June 5, 2023, 2:08 p.m. UTC 
  The following commit has been merged into the x86/mtrr branch of tip:

Commit-ID:     c957f1f3c498bcce85c04e92e60afbae1fd10cde
Gitweb:        https://git.kernel.org/tip/c957f1f3c498bcce85c04e92e60afbae1fd10cde
Author:        Juergen Gross <jgross@suse.com>
AuthorDate:    Tue, 02 May 2023 14:09:19 +02:00
Committer:     Borislav Petkov (AMD) <bp@alien8.de>
CommitterDate: Thu, 01 Jun 2023 15:04:32 +02:00

x86/hyperv: Set MTRR state when running as SEV-SNP Hyper-V guest

In order to avoid mappings using the UC- cache attribute, set the
MTRR state to use WB caching as the default.

This is needed in order to cope with the fact that PAT is enabled,
while MTRRs are not supported by the hypervisor.

Fixes: 90b926e68f50 ("x86/pat: Fix pat_x_mtrr_type() for MTRR disabled case")
Signed-off-by: Juergen Gross <jgross@suse.com>
Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de>
Tested-by: Michael Kelley <mikelley@microsoft.com>
Link: https://lore.kernel.org/r/20230502120931.20719-5-jgross@suse.com
Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de>
---
 arch/x86/hyperv/ivm.c | 4 ++++
 1 file changed, 4 insertions(+)

Comments

Michael Kelley (LINUX) June 8, 2023, 4:31 a.m. UTC | #1 
From: tip-bot2@linutronix.de <tip-bot2@linutronix.de> Sent: Monday, June 5, 2023 7:08 AM
> 
> The following commit has been merged into the x86/mtrr branch of tip:
> 
> Commit-ID:     c957f1f3c498bcce85c04e92e60afbae1fd10cde
> Gitweb:        https://git.kernel.org/pub/scm/linux/kernel/git/tip/tip.git/commit/?id=c957f1f3c498bcce85c04e92e60afbae1fd10cde
> Author:        Juergen Gross <jgross@suse.com>
> AuthorDate:    Tue, 02 May 2023 14:09:19 +02:00
> Committer:     Borislav Petkov (AMD) <bp@alien8.de>
> CommitterDate: Thu, 01 Jun 2023 15:04:32 +02:00
> 
> x86/hyperv: Set MTRR state when running as SEV-SNP Hyper-V guest
> 
> In order to avoid mappings using the UC- cache attribute, set the
> MTRR state to use WB caching as the default.
> 
> This is needed in order to cope with the fact that PAT is enabled,
> while MTRRs are not supported by the hypervisor.
> 
> Fixes: 90b926e68f50 ("x86/pat: Fix pat_x_mtrr_type() for MTRR disabled case")
> Signed-off-by: Juergen Gross <jgross@suse.com>
> Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de>
> Tested-by: Michael Kelley <mikelley@microsoft.com>
> Link: https://lore.kernel.org/all/20230502120931.20719-5-jgross@suse.com/
> Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de>
> ---
>  arch/x86/hyperv/ivm.c | 4 ++++
>  1 file changed, 4 insertions(+)
> 
> diff --git a/arch/x86/hyperv/ivm.c b/arch/x86/hyperv/ivm.c
> index cc92388..6f7c1b5 100644
> --- a/arch/x86/hyperv/ivm.c
> +++ b/arch/x86/hyperv/ivm.c
> @@ -17,6 +17,7 @@
>  #include <asm/mem_encrypt.h>
>  #include <asm/mshyperv.h>
>  #include <asm/hypervisor.h>
> +#include <asm/mtrr.h>
> 
>  #ifdef CONFIG_AMD_MEM_ENCRYPT
> 
> @@ -372,6 +373,9 @@ void __init hv_vtom_init(void)
>  	x86_platform.guest.enc_cache_flush_required = hv_vtom_cache_flush_required;
>  	x86_platform.guest.enc_tlb_flush_required = hv_vtom_tlb_flush_required;
>  	x86_platform.guest.enc_status_change_finish = hv_vtom_set_host_visibility;
> +
> +	/* Set WB as the default cache mode. */
> +	mtrr_overwrite_state(NULL, 0, MTRR_TYPE_WRBACK);
>  }
> 
>  #endif /* CONFIG_AMD_MEM_ENCRYPT */

FYI, I've tested SEV-SNP vTOM Hyper-V guests with linux-next20230607,
which includes all the MTRR changes.  Everything looks good.

Thanks!

Michael
diff mbox series

Patch

diff --git a/arch/x86/hyperv/ivm.c b/arch/x86/hyperv/ivm.c
index cc92388..6f7c1b5 100644
--- a/arch/x86/hyperv/ivm.c
+++ b/arch/x86/hyperv/ivm.c
@@ -17,6 +17,7 @@ 
 #include <asm/mem_encrypt.h>
 #include <asm/mshyperv.h>
 #include <asm/hypervisor.h>
+#include <asm/mtrr.h>
 
 #ifdef CONFIG_AMD_MEM_ENCRYPT
 
@@ -372,6 +373,9 @@  void __init hv_vtom_init(void)
 	x86_platform.guest.enc_cache_flush_required = hv_vtom_cache_flush_required;
 	x86_platform.guest.enc_tlb_flush_required = hv_vtom_tlb_flush_required;
 	x86_platform.guest.enc_status_change_finish = hv_vtom_set_host_visibility;
+
+	/* Set WB as the default cache mode. */
+	mtrr_overwrite_state(NULL, 0, MTRR_TYPE_WRBACK);
 }
 
 #endif /* CONFIG_AMD_MEM_ENCRYPT */