From patchwork Tue May 30 16:31:57 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kuogee Hsieh X-Patchwork-Id: 101001 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:994d:0:b0:3d9:f83d:47d9 with SMTP id k13csp2314727vqr; Tue, 30 May 2023 09:41:14 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ49vzW52G5g6qShbIHsChNk8cFtZq/9lib1uixzRvSX95tml9R0bEOwFCF0r0WNpgc6MVlv X-Received: by 2002:a05:6a00:993:b0:64d:277c:77d0 with SMTP id u19-20020a056a00099300b0064d277c77d0mr3219088pfg.22.1685464874257; Tue, 30 May 2023 09:41:14 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1685464874; cv=none; d=google.com; s=arc-20160816; b=roTD8BTITNRwAmmrfz88l/GVS75Y620I8qpmVufWIod2fwh83kDQtDvfbN42sVa2GJ zLGkBIun46d0+w1pTdJuObW0tk1NIqslx4AmMhbiVZ99GLwrHBbQl/WzlFmii+SiKthg 3QAaQzCor5CDuG5NPj900E2LIKLMCFKSSDcbFJXvtlGPw/mVuv03I4R9eqrr8h/HSouL PXEAeYfAuSAqLU+ZPUM/fc9C9P4m3zX5aTJyaU0eeRogGkrRr6ZiIYXgUPaeUf2LCLne s/ybUwtmbwrox7bnynsyMeC76tHiS8kUWiaLaeumxRZkUqYcjdAAmLKGtsIPF5yBhar8 6n/w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=nuNUU5PxWTALruPOf2nHBOuNO9qQlR6/ni9XgjTlAuw=; b=x1ZLiYe+vwPxDWI5Bh3dl1ZYcOjua2umG1KZTsqoLhZfOcCzmMt/7yP+j8r9wk1ve/ jBJisv1GyW8wGxw5o7y9p3bTFNrMIU9zuurW143upKxSUhE7dyoG3ceV6SiP5JvFM/RJ s+07kENXkulq6uUTArslXZv56glfC8NguU2fmKSFP7jtibW5qHsnsnJLPZPji+daCD1Y TNPSK+Oq0bHu6oQGmkr4Vm2Ix6E08/9+tZpUu+dGvmiQQ7BvTHI9yQ8SVeu22VKUemIq GJfn8qi5s7txoondNgfA+GxTNsN6+iIhmAf7J4N46FgHegimbN4kvB0i+gJe3tPrgxQs fpUA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b=TpocnICz; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id h126-20020a625384000000b0064367018c21si2001495pfb.12.2023.05.30.09.41.02; Tue, 30 May 2023 09:41:14 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b=TpocnICz; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230431AbjE3QdV (ORCPT + 99 others); Tue, 30 May 2023 12:33:21 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48066 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231401AbjE3QdQ (ORCPT ); Tue, 30 May 2023 12:33:16 -0400 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D71E5E40; Tue, 30 May 2023 09:32:42 -0700 (PDT) Received: from pps.filterd (m0279867.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 34UGLupo016810; Tue, 30 May 2023 16:32:15 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=qcppdkim1; bh=nuNUU5PxWTALruPOf2nHBOuNO9qQlR6/ni9XgjTlAuw=; b=TpocnICz/GnwvD7zBeequVWGBo8fxCzqXJW1KupHTmJ1lI5V+62Gh5064YKWX3Reqb4Y 72Z9Ribo87i9Z9ccnrmZf+J06R6doshie5HQaRUjBIknuQ+wR7vEdmUhYeCvmEwBfryG EPucIQ2mQubJteHGH/FD7UT5nY+wrQ4tPNY0fU3F1YXzwRJ4OtMUFFMYZszranFziv++ ynY1zejvNqdipzPCwUQAfoz2OC6I+UFISiOt2Zm78NgZ5Iv61Zk6ZNOOyTU2lw3Kcv/H I85xVAFi+CTDlV5CDYBffzP3NV48pE8GCIliGAIm2IBkNcHkMB5gXaH7yJckSb8qbd6n lA== Received: from nalasppmta04.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3qw5xestga-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 30 May 2023 16:32:15 +0000 Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA04.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 34UGWEVV021705 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 30 May 2023 16:32:14 GMT Received: from khsieh-linux1.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.42; Tue, 30 May 2023 09:32:13 -0700 From: Kuogee Hsieh To: , , , , , , , , , , CC: Kuogee Hsieh , , , , , , , Subject: [PATCH v1 2/3] drm/msm/dpu: retrieve DSI DSC struct at atomic_check() Date: Tue, 30 May 2023 09:31:57 -0700 Message-ID: <1685464318-25031-3-git-send-email-quic_khsieh@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1685464318-25031-1-git-send-email-quic_khsieh@quicinc.com> References: <1685464318-25031-1-git-send-email-quic_khsieh@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: RFhVdye5XFkoNYXPmiP0vGZ4VFAkYpm- X-Proofpoint-ORIG-GUID: RFhVdye5XFkoNYXPmiP0vGZ4VFAkYpm- X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.957,Hydra:6.0.573,FMLib:17.11.176.26 definitions=2023-05-30_12,2023-05-30_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 adultscore=0 malwarescore=0 bulkscore=0 priorityscore=1501 phishscore=0 spamscore=0 impostorscore=0 mlxlogscore=928 suspectscore=0 lowpriorityscore=0 mlxscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2304280000 definitions=main-2305300131 X-Spam-Status: No, score=-2.8 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_LOW,SPF_HELO_NONE, SPF_PASS,T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1767338015964471428?= X-GMAIL-MSGID: =?utf-8?q?1767338015964471428?= At current implementation, DSI DSC struct is populated at display setup during system bootup. This mechanism works fine with embedded display. But will run into problem with plugin/unplug oriented external display, such as DP, due to DSC struct will become stale once external display unplugged. New DSC struct has to be re populated to reflect newer external display which just plugged in. Move retrieving of DSI DSC struct to atomic_check() so that same mechanism will work for both embedded display and external plugin/unplug oriented display. Signed-off-by: Kuogee Hsieh --- drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 15 ++++++++++++++- drivers/gpu/drm/msm/msm_drv.h | 6 ++++++ 2 files changed, 20 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c index 3b416e1..2927d20 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c @@ -16,6 +16,8 @@ #include #include #include +#include +#include #include "msm_drv.h" #include "dpu_kms.h" @@ -639,6 +641,15 @@ static int dpu_encoder_virt_atomic_check( } } + if (dpu_enc->disp_info.intf_type == DRM_MODE_ENCODER_DSI) { + struct drm_bridge *bridge; + + if (!dpu_enc->dsc) { + bridge = drm_bridge_chain_get_first_bridge(drm_enc); + dpu_enc->dsc = msm_dsi_bridge_get_dsc_config(bridge); + } + } + topology = dpu_encoder_get_topology(dpu_enc, dpu_kms, adj_mode, crtc_state); /* @@ -2121,8 +2132,10 @@ void dpu_encoder_helper_phys_cleanup(struct dpu_encoder_phys *phys_enc) phys_enc->hw_pp->merge_3d->idx); } - if (dpu_enc->dsc) + if (dpu_enc->dsc) { dpu_encoder_unprep_dsc(dpu_enc); + dpu_enc->dsc = NULL; + } intf_cfg.stream_sel = 0; /* Don't care value for video mode */ intf_cfg.mode_3d = dpu_encoder_helper_get_3d_blend_mode(phys_enc); diff --git a/drivers/gpu/drm/msm/msm_drv.h b/drivers/gpu/drm/msm/msm_drv.h index e13a8cb..5a7c1f4 100644 --- a/drivers/gpu/drm/msm/msm_drv.h +++ b/drivers/gpu/drm/msm/msm_drv.h @@ -341,6 +341,7 @@ bool msm_dsi_is_cmd_mode(struct msm_dsi *msm_dsi); bool msm_dsi_is_bonded_dsi(struct msm_dsi *msm_dsi); bool msm_dsi_is_master_dsi(struct msm_dsi *msm_dsi); struct drm_dsc_config *msm_dsi_get_dsc_config(struct msm_dsi *msm_dsi); +struct drm_dsc_config *msm_dsi_bridge_get_dsc_config(struct drm_bridge *bridge); #else static inline void __init msm_dsi_register(void) { @@ -374,6 +375,11 @@ static inline struct drm_dsc_config *msm_dsi_get_dsc_config(struct msm_dsi *msm_ { return NULL; } + +struct drm_dsc_config *msm_dsi_bridge_get_dsc_config(struct drm_bridge *bridge) +{ + return NULL; +} #endif #ifdef CONFIG_DRM_MSM_DP