diff mbox series

[GIT,pull] perf/urgent for 6.4-rc4

Message ID 168526035979.3457722.10299010241065106864.tglx@xen13
State New
Headers
Series [GIT,pull] perf/urgent for 6.4-rc4 |

Commit Message

Thomas Gleixner May 28, 2023, 7:53 a.m. UTC 
  Linus,

please pull the latest perf/urgent branch from:

   git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip.git perf-urgent-2023-05-28

up to:  38776cc45eb7: perf/x86/uncore: Correct the number of CHAs on SPR


A small set of perf fixes:

 - Make the CHA discovery based on MSR readout to work around broken
   discovery tables in some SPR firmwares.

 - Prevent saving PEBS configuration which has software bits set that
   cause a crash when restored into the relevant MSR.

Thanks,

	tglx

------------------>
Kan Liang (1):
      perf/x86/uncore: Correct the number of CHAs on SPR

Like Xu (1):
      perf/x86/intel: Save/restore cpuc->active_pebs_data_cfg when using guest PEBS


 arch/x86/events/intel/core.c         |  2 +-
 arch/x86/events/intel/uncore_snbep.c | 11 +++++++++++
 2 files changed, 12 insertions(+), 1 deletion(-)

Comments

pr-tracker-bot@kernel.org May 28, 2023, 11:46 a.m. UTC | #1 
The pull request you sent on Sun, 28 May 2023 09:53:00 +0200 (CEST):

> git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip.git perf-urgent-2023-05-28

has been merged into torvalds/linux.git:
https://git.kernel.org/torvalds/c/2d5438f4c6fdaa34c5d7de89a5331b8dbcd920af

Thank you!
diff mbox series

Patch

diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c
index 070cc4ef2672..89b9c1cebb61 100644
--- a/arch/x86/events/intel/core.c
+++ b/arch/x86/events/intel/core.c
@@ -4074,7 +4074,7 @@  static struct perf_guest_switch_msr *intel_guest_get_msrs(int *nr, void *data)
 	if (x86_pmu.intel_cap.pebs_baseline) {
 		arr[(*nr)++] = (struct perf_guest_switch_msr){
 			.msr = MSR_PEBS_DATA_CFG,
-			.host = cpuc->pebs_data_cfg,
+			.host = cpuc->active_pebs_data_cfg,
 			.guest = kvm_pmu->pebs_data_cfg,
 		};
 	}
diff --git a/arch/x86/events/intel/uncore_snbep.c b/arch/x86/events/intel/uncore_snbep.c
index fa9b209a11fa..d49e90dc04a4 100644
--- a/arch/x86/events/intel/uncore_snbep.c
+++ b/arch/x86/events/intel/uncore_snbep.c
@@ -6150,6 +6150,7 @@  static struct intel_uncore_type spr_uncore_mdf = {
 };
 
 #define UNCORE_SPR_NUM_UNCORE_TYPES		12
+#define UNCORE_SPR_CHA				0
 #define UNCORE_SPR_IIO				1
 #define UNCORE_SPR_IMC				6
 #define UNCORE_SPR_UPI				8
@@ -6460,12 +6461,22 @@  static int uncore_type_max_boxes(struct intel_uncore_type **types,
 	return max + 1;
 }
 
+#define SPR_MSR_UNC_CBO_CONFIG		0x2FFE
+
 void spr_uncore_cpu_init(void)
 {
+	struct intel_uncore_type *type;
+	u64 num_cbo;
+
 	uncore_msr_uncores = uncore_get_uncores(UNCORE_ACCESS_MSR,
 						UNCORE_SPR_MSR_EXTRA_UNCORES,
 						spr_msr_uncores);
 
+	type = uncore_find_type_by_id(uncore_msr_uncores, UNCORE_SPR_CHA);
+	if (type) {
+		rdmsrl(SPR_MSR_UNC_CBO_CONFIG, num_cbo);
+		type->num_boxes = num_cbo;
+	}
 	spr_uncore_iio_free_running.num_boxes = uncore_type_max_boxes(uncore_msr_uncores, UNCORE_SPR_IIO);
 }