diff mbox series

[tip:,perf/urgent] perf/x86/uncore: Correct the number of CHAs on SPR

Message ID 168500626995.404.15734964484046172688.tip-bot2@tip-bot2
State New
Headers
Series [tip:,perf/urgent] perf/x86/uncore: Correct the number of CHAs on SPR |

Commit Message

tip-bot2 for Thomas Gleixner May 25, 2023, 9:17 a.m. UTC 
  The following commit has been merged into the perf/urgent branch of tip:

Commit-ID:     38776cc45eb7603df4735a0410f42cffff8e71a1
Gitweb:        https://git.kernel.org/tip/38776cc45eb7603df4735a0410f42cffff8e71a1
Author:        Kan Liang <kan.liang@linux.intel.com>
AuthorDate:    Mon, 08 May 2023 07:02:06 -07:00
Committer:     Peter Zijlstra <peterz@infradead.org>
CommitterDate: Wed, 24 May 2023 22:19:41 +02:00

perf/x86/uncore: Correct the number of CHAs on SPR

The number of CHAs from the discovery table on some SPR variants is
incorrect, because of a firmware issue. An accurate number can be read
from the MSR UNC_CBO_CONFIG.

Fixes: 949b11381f81 ("perf/x86/intel/uncore: Add Sapphire Rapids server CHA support")
Reported-by: Stephane Eranian <eranian@google.com>
Signed-off-by: Kan Liang <kan.liang@linux.intel.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Tested-by: Stephane Eranian <eranian@google.com>
Cc: stable@vger.kernel.org
Link: https://lore.kernel.org/r/20230508140206.283708-1-kan.liang@linux.intel.com
---
 arch/x86/events/intel/uncore_snbep.c | 11 +++++++++++
 1 file changed, 11 insertions(+)
diff mbox series

Patch

diff --git a/arch/x86/events/intel/uncore_snbep.c b/arch/x86/events/intel/uncore_snbep.c
index fa9b209..d49e90d 100644
--- a/arch/x86/events/intel/uncore_snbep.c
+++ b/arch/x86/events/intel/uncore_snbep.c
@@ -6150,6 +6150,7 @@  static struct intel_uncore_type spr_uncore_mdf = {
 };
 
 #define UNCORE_SPR_NUM_UNCORE_TYPES		12
+#define UNCORE_SPR_CHA				0
 #define UNCORE_SPR_IIO				1
 #define UNCORE_SPR_IMC				6
 #define UNCORE_SPR_UPI				8
@@ -6460,12 +6461,22 @@  static int uncore_type_max_boxes(struct intel_uncore_type **types,
 	return max + 1;
 }
 
+#define SPR_MSR_UNC_CBO_CONFIG		0x2FFE
+
 void spr_uncore_cpu_init(void)
 {
+	struct intel_uncore_type *type;
+	u64 num_cbo;
+
 	uncore_msr_uncores = uncore_get_uncores(UNCORE_ACCESS_MSR,
 						UNCORE_SPR_MSR_EXTRA_UNCORES,
 						spr_msr_uncores);
 
+	type = uncore_find_type_by_id(uncore_msr_uncores, UNCORE_SPR_CHA);
+	if (type) {
+		rdmsrl(SPR_MSR_UNC_CBO_CONFIG, num_cbo);
+		type->num_boxes = num_cbo;
+	}
 	spr_uncore_iio_free_running.num_boxes = uncore_type_max_boxes(uncore_msr_uncores, UNCORE_SPR_IIO);
 }