[irqchip:,irq/irqchip-next] RISC-V: Clear SIP bit only when using SBI IPI operations
Commit Message
The following commit has been merged into the irq/irqchip-next branch of irqchip:
Commit-ID: 3ee92565b83ecc08e5b0c878dd87a2973eaca2ea
Gitweb: https://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms/3ee92565b83ecc08e5b0c878dd87a2973eaca2ea
Author: Anup Patel <apatel@ventanamicro.com>
AuthorDate: Tue, 28 Mar 2023 09:22:17 +05:30
Committer: Marc Zyngier <maz@kernel.org>
CommitterDate: Sat, 08 Apr 2023 11:26:23 +01:00
RISC-V: Clear SIP bit only when using SBI IPI operations
The software interrupt pending (i.e. [M|S]SIP) bit is writeable for
S-mode but read-only for M-mode so we clear this bit only when using
SBI IPI operations.
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Atish Patra <atishp@rivosinc.com>
Acked-by: Palmer Dabbelt <palmer@rivosinc.com>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20230328035223.1480939-2-apatel@ventanamicro.com
---
arch/riscv/kernel/sbi.c | 8 +++++++-
arch/riscv/kernel/smp.c | 2 --
2 files changed, 7 insertions(+), 3 deletions(-)
@@ -646,8 +646,14 @@ static void sbi_send_cpumask_ipi(const struct cpumask *target)
sbi_send_ipi(target);
}
+static void sbi_ipi_clear(void)
+{
+ csr_clear(CSR_IP, IE_SIE);
+}
+
static const struct riscv_ipi_ops sbi_ipi_ops = {
- .ipi_inject = sbi_send_cpumask_ipi
+ .ipi_inject = sbi_send_cpumask_ipi,
+ .ipi_clear = sbi_ipi_clear
};
void __init sbi_init(void)
@@ -112,8 +112,6 @@ void riscv_clear_ipi(void)
{
if (ipi_ops && ipi_ops->ipi_clear)
ipi_ops->ipi_clear();
-
- csr_clear(CSR_IP, IE_SIE);
}
EXPORT_SYMBOL_GPL(riscv_clear_ipi);