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[tip:,x86/apic] x86/apic: Fix atomic update of offset in reserve_eilvt_offset()

Message ID 168087299261.404.3541260516013039940.tip-bot2@tip-bot2
State New
Headers
Series [tip:,x86/apic] x86/apic: Fix atomic update of offset in reserve_eilvt_offset() |

Commit Message

tip-bot2 for Thomas Gleixner April 7, 2023, 1:09 p.m. UTC 
  The following commit has been merged into the x86/apic branch of tip:

Commit-ID:     f96fb2df3eb31ede1b34b0521560967310267750
Gitweb:        https://git.kernel.org/tip/f96fb2df3eb31ede1b34b0521560967310267750
Author:        Uros Bizjak <ubizjak@gmail.com>
AuthorDate:    Mon, 27 Feb 2023 17:09:17 +01:00
Committer:     Borislav Petkov (AMD) <bp@alien8.de>
CommitterDate: Fri, 07 Apr 2023 14:34:24 +02:00

x86/apic: Fix atomic update of offset in reserve_eilvt_offset()

The detection of atomic update failure in reserve_eilvt_offset() is
not correct. The value returned by atomic_cmpxchg() should be compared
to the old value from the location to be updated.

If these two are the same, then atomic update succeeded and
"eilvt_offsets[offset]" location is updated to "new" in an atomic way.

Otherwise, the atomic update failed and it should be retried with the
value from "eilvt_offsets[offset]" - exactly what atomic_try_cmpxchg()
does in a correct and more optimal way.

Fixes: a68c439b1966c ("apic, x86: Check if EILVT APIC registers are available (AMD only)")
Signed-off-by: Uros Bizjak <ubizjak@gmail.com>
Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de>
Link: https://lore.kernel.org/r/20230227160917.107820-1-ubizjak@gmail.com
---
 arch/x86/kernel/apic/apic.c | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)
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Patch

diff --git a/arch/x86/kernel/apic/apic.c b/arch/x86/kernel/apic/apic.c
index 20d9a60..7705571 100644
--- a/arch/x86/kernel/apic/apic.c
+++ b/arch/x86/kernel/apic/apic.c
@@ -422,10 +422,9 @@  static unsigned int reserve_eilvt_offset(int offset, unsigned int new)
 		if (vector && !eilvt_entry_is_changeable(vector, new))
 			/* may not change if vectors are different */
 			return rsvd;
-		rsvd = atomic_cmpxchg(&eilvt_offsets[offset], rsvd, new);
-	} while (rsvd != new);
+	} while (!atomic_try_cmpxchg(&eilvt_offsets[offset], &rsvd, new));
 
-	rsvd &= ~APIC_EILVT_MASKED;
+	rsvd = new & ~APIC_EILVT_MASKED;
 	if (rsvd && rsvd != vector)
 		pr_info("LVT offset %d assigned for vector 0x%02x\n",
 			offset, rsvd);