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[2620:137:e000::1:20]) by mx.google.com with ESMTP id pg17-20020a170907205100b0092fd56751ffsi30702498ejb.420.2023.03.29.01.00.44; Wed, 29 Mar 2023 01:01:10 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b=JhLZb4eo; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230075AbjC2Hr2 (ORCPT + 99 others); Wed, 29 Mar 2023 03:47:28 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33826 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230053AbjC2HrT (ORCPT ); Wed, 29 Mar 2023 03:47:19 -0400 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2AFF335A2; Wed, 29 Mar 2023 00:47:19 -0700 (PDT) Received: from pps.filterd (m0279871.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 32T2l95N017029; Wed, 29 Mar 2023 07:47:10 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=qcppdkim1; bh=nOAvH2qE72J+9pGBrgAidXdZmAdy3OZE8caa/4T+p7w=; b=JhLZb4eo3LcmkTFHYtYuWZ9as22PtiKOO6xFQQwy7egx+L8zxFVgYdkOyo10SJ9Zj1/X gSfwj67/Fd3fGamw9UzSUCZpDU1RjiXJu6sd4IEZ1CIo+W1/aT6VPcNaAU9VaMnj0gtk hI8nZA1p4Qu4oKo26WxKBQooZ/3Zo55sGDcKiUs/1GQU/lP5kOtX72fp7axCJTbmQtqU lPTJ2Ntq2JcdH4vkIVVHLk9eydHb56wODp25wNevvTNJ5UDCWkO4XeoXwSKp6TmmV+0q 986/7fthcV5ZhVa61vV1pCggasUFbrzyRerl0XOpL5b1N+tohihgg8ndVCAcwnHuuOpm aQ== Received: from nasanppmta05.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3pkx0ftty9-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 29 Mar 2023 07:47:10 +0000 Received: from nasanex01c.na.qualcomm.com (nasanex01c.na.qualcomm.com [10.45.79.139]) by NASANPPMTA05.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 32T7l9kS023692 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 29 Mar 2023 07:47:09 GMT Received: from hu-mojha-hyd.qualcomm.com (10.80.80.8) by nasanex01c.na.qualcomm.com (10.45.79.139) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.42; Wed, 29 Mar 2023 00:47:06 -0700 From: Mukesh Ojha To: , , , CC: , , , Mukesh Ojha Subject: [PATCH v6 1/5] firmware: qcom_scm: provide a read-modify-write function Date: Wed, 29 Mar 2023 13:16:48 +0530 Message-ID: <1680076012-10785-2-git-send-email-quic_mojha@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1680076012-10785-1-git-send-email-quic_mojha@quicinc.com> References: <1680076012-10785-1-git-send-email-quic_mojha@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nasanex01c.na.qualcomm.com (10.45.79.139) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: 7RlvtKQieLUnk52DAQDsOApBEzTLBm5O X-Proofpoint-GUID: 7RlvtKQieLUnk52DAQDsOApBEzTLBm5O X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.942,Hydra:6.0.573,FMLib:17.11.170.22 definitions=2023-03-29_02,2023-03-28_02,2023-02-09_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 malwarescore=0 adultscore=0 impostorscore=0 suspectscore=0 lowpriorityscore=0 mlxscore=0 clxscore=1015 bulkscore=0 mlxlogscore=646 priorityscore=1501 spamscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2303200000 definitions=main-2303290063 X-Spam-Status: No, score=-0.2 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1761688284384130689?= X-GMAIL-MSGID: =?utf-8?q?1761688284384130689?= It was realized by Srinivas K. that there is a need of read-modify-write scm exported function so that it can be used by multiple clients. Let's introduce qcom_scm_io_update_field() which masks out the bits and write the passed value to that bit-offset. Subsequent patch will use this function. Suggested-by: Srinivas Kandagatla Signed-off-by: Mukesh Ojha --- drivers/firmware/qcom_scm.c | 15 +++++++++++++++ include/linux/firmware/qcom/qcom_scm.h | 2 ++ 2 files changed, 17 insertions(+) diff --git a/drivers/firmware/qcom_scm.c b/drivers/firmware/qcom_scm.c index 5f281cb..cb0bc32 100644 --- a/drivers/firmware/qcom_scm.c +++ b/drivers/firmware/qcom_scm.c @@ -407,6 +407,21 @@ int qcom_scm_set_remote_state(u32 state, u32 id) } EXPORT_SYMBOL(qcom_scm_set_remote_state); +int qcom_scm_io_update_field(phys_addr_t addr, unsigned int mask, unsigned int val) +{ + unsigned int old, new; + int ret; + + ret = qcom_scm_io_readl(addr, &old); + if (ret) + return ret; + + new = (old & ~mask) | val << (ffs(mask) - 1); + + return qcom_scm_io_writel(addr, new); +} +EXPORT_SYMBOL(qcom_scm_io_update_field); + static int __qcom_scm_set_dload_mode(struct device *dev, bool enable) { struct qcom_scm_desc desc = { diff --git a/include/linux/firmware/qcom/qcom_scm.h b/include/linux/firmware/qcom/qcom_scm.h index 1e449a5..203a781 100644 --- a/include/linux/firmware/qcom/qcom_scm.h +++ b/include/linux/firmware/qcom/qcom_scm.h @@ -84,6 +84,8 @@ extern bool qcom_scm_pas_supported(u32 peripheral); extern int qcom_scm_io_readl(phys_addr_t addr, unsigned int *val); extern int qcom_scm_io_writel(phys_addr_t addr, unsigned int val); +extern int qcom_scm_io_update_field(phys_addr_t addr, unsigned int mask, + unsigned int val); extern bool qcom_scm_restore_sec_cfg_available(void); extern int qcom_scm_restore_sec_cfg(u32 device_id, u32 spare);