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[2620:137:e000::1:20]) by mx.google.com with ESMTP id v30-20020aa799de000000b0062d90384500si3194709pfi.307.2023.03.28.09.08.42; Tue, 28 Mar 2023 09:08:59 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b=MtuOlzOq; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234050AbjC1Plg (ORCPT + 99 others); Tue, 28 Mar 2023 11:41:36 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46928 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233729AbjC1PlO (ORCPT ); Tue, 28 Mar 2023 11:41:14 -0400 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1D5B011674; Tue, 28 Mar 2023 08:40:13 -0700 (PDT) Received: from pps.filterd (m0279873.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 32SAsU6b014641; Tue, 28 Mar 2023 15:39:50 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=qcppdkim1; bh=nOAvH2qE72J+9pGBrgAidXdZmAdy3OZE8caa/4T+p7w=; b=MtuOlzOqMLiBtiQBF+u5vUmSjXY3zVomFQq7M6nySKzknyNAdD4ecwfiBbHZS1jZajYJ X+nbqMPw1uA5q64gOAN0owWuBcaVbhzRRrWnTjaOpLIV6he3R2O2bKV6yQOJV+nfXkbe u//GJhIHlNj00Mx64eR1EgLfB3PV4u/WL6AjVbKhs019J531CqkCas9qyH0Mx6ZcNY0X gwrIgLY5ndBt6R/MnfcsKeHcvWm3zIvh0MqtsTPuzw/w7jTPcf0IP+AGHuW68n7UEQ6N YNZa0SLPkRLunqYDCEQ8xjjfZA3O7qNPuDbKU5ygoEQT8C5ORjwRKMix/VjZCCAUGlks aA== Received: from nasanppmta04.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3pkv45h8gm-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 28 Mar 2023 15:39:50 +0000 Received: from nasanex01c.na.qualcomm.com (nasanex01c.na.qualcomm.com [10.45.79.139]) by NASANPPMTA04.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 32SFdnoo004663 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 28 Mar 2023 15:39:49 GMT Received: from hu-mojha-hyd.qualcomm.com (10.80.80.8) by nasanex01c.na.qualcomm.com (10.45.79.139) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.42; Tue, 28 Mar 2023 08:39:46 -0700 From: Mukesh Ojha To: , , , CC: , , , Mukesh Ojha Subject: [PATCH v5 1/5] firmware: qcom_scm: provide a read-modify-write function Date: Tue, 28 Mar 2023 21:07:45 +0530 Message-ID: <1680017869-22421-2-git-send-email-quic_mojha@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1680017869-22421-1-git-send-email-quic_mojha@quicinc.com> References: <1680017869-22421-1-git-send-email-quic_mojha@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nasanex01c.na.qualcomm.com (10.45.79.139) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: yhExNJi0zq4kd0jlKCn3f4i02nenOIXD X-Proofpoint-ORIG-GUID: yhExNJi0zq4kd0jlKCn3f4i02nenOIXD X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.942,Hydra:6.0.573,FMLib:17.11.170.22 definitions=2023-03-24_11,2023-03-28_02,2023-02-09_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 phishscore=0 spamscore=0 lowpriorityscore=0 adultscore=0 malwarescore=0 suspectscore=0 bulkscore=0 impostorscore=0 clxscore=1015 mlxlogscore=646 mlxscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2303200000 definitions=main-2303280121 X-Spam-Status: No, score=-0.2 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1761628378672631133?= X-GMAIL-MSGID: =?utf-8?q?1761628378672631133?= It was realized by Srinivas K. that there is a need of read-modify-write scm exported function so that it can be used by multiple clients. Let's introduce qcom_scm_io_update_field() which masks out the bits and write the passed value to that bit-offset. Subsequent patch will use this function. Suggested-by: Srinivas Kandagatla Signed-off-by: Mukesh Ojha --- drivers/firmware/qcom_scm.c | 15 +++++++++++++++ include/linux/firmware/qcom/qcom_scm.h | 2 ++ 2 files changed, 17 insertions(+) diff --git a/drivers/firmware/qcom_scm.c b/drivers/firmware/qcom_scm.c index 5f281cb..cb0bc32 100644 --- a/drivers/firmware/qcom_scm.c +++ b/drivers/firmware/qcom_scm.c @@ -407,6 +407,21 @@ int qcom_scm_set_remote_state(u32 state, u32 id) } EXPORT_SYMBOL(qcom_scm_set_remote_state); +int qcom_scm_io_update_field(phys_addr_t addr, unsigned int mask, unsigned int val) +{ + unsigned int old, new; + int ret; + + ret = qcom_scm_io_readl(addr, &old); + if (ret) + return ret; + + new = (old & ~mask) | val << (ffs(mask) - 1); + + return qcom_scm_io_writel(addr, new); +} +EXPORT_SYMBOL(qcom_scm_io_update_field); + static int __qcom_scm_set_dload_mode(struct device *dev, bool enable) { struct qcom_scm_desc desc = { diff --git a/include/linux/firmware/qcom/qcom_scm.h b/include/linux/firmware/qcom/qcom_scm.h index 1e449a5..203a781 100644 --- a/include/linux/firmware/qcom/qcom_scm.h +++ b/include/linux/firmware/qcom/qcom_scm.h @@ -84,6 +84,8 @@ extern bool qcom_scm_pas_supported(u32 peripheral); extern int qcom_scm_io_readl(phys_addr_t addr, unsigned int *val); extern int qcom_scm_io_writel(phys_addr_t addr, unsigned int val); +extern int qcom_scm_io_update_field(phys_addr_t addr, unsigned int mask, + unsigned int val); extern bool qcom_scm_restore_sec_cfg_available(void); extern int qcom_scm_restore_sec_cfg(u32 device_id, u32 spare);