diff mbox series

[tip:,x86/misc] tools/x86/kcpuid: Fix avx512bw and avx512lvl fields in Fn00000007

Message ID 167822889104.5837.1505725503143263010.tip-bot2@tip-bot2
State New
Headers
Series [tip:,x86/misc] tools/x86/kcpuid: Fix avx512bw and avx512lvl fields in Fn00000007 |

Commit Message

tip-bot2 for Thomas Gleixner March 7, 2023, 10:41 p.m. UTC 
  The following commit has been merged into the x86/misc branch of tip:

Commit-ID:     4e347bdf44c1fd4296a7b9657a2c0e1bd900fa50
Gitweb:        https://git.kernel.org/tip/4e347bdf44c1fd4296a7b9657a2c0e1bd900fa50
Author:        Terry Bowman <terry.bowman@amd.com>
AuthorDate:    Mon, 06 Feb 2023 08:18:30 -06:00
Committer:     Borislav Petkov (AMD) <bp@alien8.de>
CommitterDate: Tue, 07 Mar 2023 23:27:07 +01:00

tools/x86/kcpuid: Fix avx512bw and avx512lvl fields in Fn00000007

Leaf Fn00000007 contains avx512bw at bit 26 and avx512vl at bit 28. This
is incorrect per the SDM. Correct avx512bw to be bit 30 and avx512lvl to
be bit 31.

Fixes: c6b2f240bf8d ("tools/x86: Add a kcpuid tool to show raw CPU features")
Signed-off-by: Terry Bowman <terry.bowman@amd.com>
Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de>
Reviewed-by: Feng Tang <feng.tang@intel.com>
Link: https://lore.kernel.org/r/20230206141832.4162264-2-terry.bowman@amd.com
---
 tools/arch/x86/kcpuid/cpuid.csv | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)
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Patch

diff --git a/tools/arch/x86/kcpuid/cpuid.csv b/tools/arch/x86/kcpuid/cpuid.csv
index 4f1c4b0..9914bdf 100644
--- a/tools/arch/x86/kcpuid/cpuid.csv
+++ b/tools/arch/x86/kcpuid/cpuid.csv
@@ -184,8 +184,8 @@ 
 	 7,    0,  EBX,     27, avx512er, AVX512 Exponent Reciproca instr
 	 7,    0,  EBX,     28, avx512cd, AVX512 Conflict Detection instr
 	 7,    0,  EBX,     29, sha, Intel Secure Hash Algorithm Extensions instr
-	 7,    0,  EBX,     26, avx512bw, AVX512 Byte & Word instr
-	 7,    0,  EBX,     28, avx512vl, AVX512 Vector Length Extentions (VL)
+	 7,    0,  EBX,     30, avx512bw, AVX512 Byte & Word instr
+	 7,    0,  EBX,     31, avx512vl, AVX512 Vector Length Extentions (VL)
 	 7,    0,  ECX,      0, prefetchwt1, X
 	 7,    0,  ECX,      1, avx512vbmi, AVX512 Vector Byte Manipulation Instructions
 	 7,    0,  ECX,      2, umip, User-mode Instruction Prevention