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Mon, 06 Mar 2023 05:25:09 +0000 Received: from pps.filterd (APBLRPPMTA01.qualcomm.com [127.0.0.1]) by APBLRPPMTA01.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTP id 3265P6UW016105; Mon, 6 Mar 2023 05:25:06 GMT Received: from pps.reinject (localhost [127.0.0.1]) by APBLRPPMTA01.qualcomm.com (PPS) with ESMTPS id 3p4fgk739p-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NO); Mon, 06 Mar 2023 05:25:06 +0000 Received: from APBLRPPMTA01.qualcomm.com (APBLRPPMTA01.qualcomm.com [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 3265P6ZA016088; Mon, 6 Mar 2023 05:25:06 GMT Received: from hu-sgudaval-hyd.qualcomm.com (hu-rohiagar-hyd.qualcomm.com [10.213.106.138]) by APBLRPPMTA01.qualcomm.com (PPS) with ESMTP id 3265P5hi016079; Mon, 06 Mar 2023 05:25:06 +0000 Received: by hu-sgudaval-hyd.qualcomm.com (Postfix, from userid 3970568) id 3F3144F8A; Mon, 6 Mar 2023 10:55:05 +0530 (+0530) From: Rohit Agarwal To: agross@kernel.org, andersson@kernel.org, konrad.dybcio@linaro.org, lee@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, mani@kernel.org, lpieralisi@kernel.org, kw@linux.com, bhelgaas@google.com, manivannan.sadhasivam@linaro.org Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, Rohit Agarwal Subject: [PATCH 3/6] ARM: dts: qcom: sdx65: Add support for PCIe PHY Date: Mon, 6 Mar 2023 10:54:59 +0530 Message-Id: <1678080302-29691-4-git-send-email-quic_rohiagar@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1678080302-29691-1-git-send-email-quic_rohiagar@quicinc.com> References: <1678080302-29691-1-git-send-email-quic_rohiagar@quicinc.com> X-QCInternal: smtphost X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: 2PbY9edJb04vOzPaAyXWflP3YUfpnbtG X-Proofpoint-GUID: 2PbY9edJb04vOzPaAyXWflP3YUfpnbtG X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.219,Aquarius:18.0.942,Hydra:6.0.573,FMLib:17.11.170.22 definitions=2023-03-05_12,2023-03-03_01,2023-02-09_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 mlxscore=0 impostorscore=0 clxscore=1015 suspectscore=0 lowpriorityscore=0 phishscore=0 adultscore=0 malwarescore=0 priorityscore=1501 mlxlogscore=999 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2212070000 definitions=main-2303060044 X-Spam-Status: No, score=-2.4 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, RCVD_IN_DNSWL_LOW,SPF_HELO_NONE,SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1759594945495421832?= X-GMAIL-MSGID: =?utf-8?q?1759594945495421832?= Add devicetree support for PCIe PHY used in SDX65 platform. This PHY is used by the PCIe EP controller. Signed-off-by: Rohit Agarwal --- arch/arm/boot/dts/qcom-sdx65.dtsi | 32 ++++++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+) diff --git a/arch/arm/boot/dts/qcom-sdx65.dtsi b/arch/arm/boot/dts/qcom-sdx65.dtsi index b073e0c..246290d 100644 --- a/arch/arm/boot/dts/qcom-sdx65.dtsi +++ b/arch/arm/boot/dts/qcom-sdx65.dtsi @@ -292,6 +292,38 @@ status = "disabled"; }; + pcie0_phy: phy@1c07000 { + compatible = "qcom,sdx65-qmp-pcie-phy"; + reg = <0x01c07000 0x1e4>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + clocks = <&gcc GCC_PCIE_AUX_PHY_CLK_SRC>, + <&gcc GCC_PCIE_CFG_AHB_CLK>, + <&gcc GCC_PCIE_0_CLKREF_EN>, + <&gcc GCC_PCIE_RCHNG_PHY_CLK>; + clock-names = "aux", "cfg_ahb", "ref", "refgen"; + + resets = <&gcc GCC_PCIE_PHY_BCR>; + reset-names = "phy"; + assigned-clocks = <&gcc GCC_PCIE_RCHNG_PHY_CLK>; + assigned-clock-rates = <100000000>; + status = "disabled"; + + pcie0_lane: lanes@1c06000 { + reg = <0x01c06000 0xf0>, /* tx0 */ + <0x01c06200 0x2f0>, /* rx0 */ + <0x01c07200 0x1e8>, /* pcs */ + <0x01c06800 0xf0>, /* tx1 */ + <0x01c06a00 0x2f0>, /* rx1 */ + <0x01c07400 0xc00>; /* pcs_misc */ + clocks = <&gcc GCC_PCIE_PIPE_CLK>; + clock-names = "pipe0"; + #phy-cells = <0>; + clock-output-names = "pcie_pipe_clk"; + }; + }; + tcsr_mutex: hwlock@1f40000 { compatible = "qcom,tcsr-mutex"; reg = <0x01f40000 0x40000>;