diff mbox series

[tip:,timers/core] dt-bindings: timer: sifive,clint: add comaptibles for T-Head's C9xx

Message ID 167631278317.4906.9154845972759763827.tip-bot2@tip-bot2
State New
Headers
Series [tip:,timers/core] dt-bindings: timer: sifive,clint: add comaptibles for T-Head's C9xx |

Commit Message

tip-bot2 for Thomas Gleixner Feb. 13, 2023, 6:26 p.m. UTC 
  The following commit has been merged into the timers/core branch of tip:

Commit-ID:     abd873afc889c0b4348ec4b567d83f97df8edaf6
Gitweb:        https://git.kernel.org/tip/abd873afc889c0b4348ec4b567d83f97df8edaf6
Author:        Icenowy Zheng <uwu@icenowy.me>
AuthorDate:    Thu, 02 Feb 2023 15:28:14 +08:00
Committer:     Daniel Lezcano <daniel.lezcano@linaro.org>
CommitterDate: Mon, 13 Feb 2023 13:10:17 +01:00

dt-bindings: timer: sifive,clint: add comaptibles for T-Head's C9xx

T-Head C906/C910 CLINT is not compliant to SiFive ones (and even not
compliant to the newcoming ACLINT spec) because of lack of mtime
register.

Add a compatible string formatted like the C9xx-specific PLIC
compatible, and do not allow a SiFive one as fallback because they're
not really compliant.

Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Samuel Holland <samuel@sholland.org>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20230202072814.319903-1-uwu@icenowy.me
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
---
 Documentation/devicetree/bindings/timer/sifive,clint.yaml | 8 +++++++-
 1 file changed, 8 insertions(+)
diff mbox series

Patch

diff --git a/Documentation/devicetree/bindings/timer/sifive,clint.yaml b/Documentation/devicetree/bindings/timer/sifive,clint.yaml
index bbad241..aada695 100644
--- a/Documentation/devicetree/bindings/timer/sifive,clint.yaml
+++ b/Documentation/devicetree/bindings/timer/sifive,clint.yaml
@@ -20,6 +20,10 @@  description:
   property of "/cpus" DT node. The "timebase-frequency" DT property is
   described in Documentation/devicetree/bindings/riscv/cpus.yaml
 
+  T-Head C906/C910 CPU cores include an implementation of CLINT too, however
+  their implementation lacks a memory-mapped MTIME register, thus not
+  compatible with SiFive ones.
+
 properties:
   compatible:
     oneOf:
@@ -30,6 +34,10 @@  properties:
               - canaan,k210-clint
           - const: sifive,clint0
       - items:
+          - enum:
+              - allwinner,sun20i-d1-clint
+          - const: thead,c900-clint
+      - items:
           - const: sifive,clint0
           - const: riscv,clint0
         deprecated: true