diff mbox series

[v5,04/14] arm64: dts: Add i.MX8MM PCIe EP support

Message ID 1673847684-31893-5-git-send-email-hongxing.zhu@nxp.com
State New
Headers
Series Add i.MX PCIe EP mode support |

Commit Message

Richard Zhu Jan. 16, 2023, 5:41 a.m. UTC 
  Add i.MX8MM PCIe EP support.

Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
---
 arch/arm64/boot/dts/freescale/imx8mm.dtsi | 20 ++++++++++++++++++++
 1 file changed, 20 insertions(+)

Comments

Shawn Guo Jan. 26, 2023, 6:47 a.m. UTC | #1 
On Mon, Jan 16, 2023 at 01:41:14PM +0800, Richard Zhu wrote:
> Add i.MX8MM PCIe EP support.
> 
> Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
> ---
>  arch/arm64/boot/dts/freescale/imx8mm.dtsi | 20 ++++++++++++++++++++
>  1 file changed, 20 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
> index 4ee89fdcf59b..8124761f629c 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
> @@ -1293,6 +1293,26 @@ pcie0: pcie@33800000 {
>  			status = "disabled";
>  		};
>  
> +		pcie0_ep: pcie_ep@33800000 {

Hyphen is more preferable than underscore in name node.

I fixed it (and the other two patches) up, and applied all DTS patches.

Shawn

> +			compatible = "fsl,imx8mm-pcie-ep";
> +			reg = <0x33800000 0x400000>,
> +			      <0x18000000 0x8000000>;
> +			reg-names = "regs", "addr_space";
> +			num-lanes = <1>;
> +			interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
> +			interrupt-names = "dma";
> +			fsl,max-link-speed = <2>;
> +			power-domains = <&pgc_pcie>;
> +			resets = <&src IMX8MQ_RESET_PCIE_CTRL_APPS_EN>,
> +				 <&src IMX8MQ_RESET_PCIE_CTRL_APPS_TURNOFF>;
> +			reset-names = "apps", "turnoff";
> +			phys = <&pcie_phy>;
> +			phy-names = "pcie-phy";
> +			num-ib-windows = <4>;
> +			num-ob-windows = <4>;
> +			status = "disabled";
> +		};
> +
>  		gpu_3d: gpu@38000000 {
>  			compatible = "vivante,gc";
>  			reg = <0x38000000 0x8000>;
> -- 
> 2.25.1
>
Shawn Guo Jan. 26, 2023, 8:37 a.m. UTC | #2 
On Thu, Jan 26, 2023 at 2:47 PM Shawn Guo <shawnguo@kernel.org> wrote:
>
> On Mon, Jan 16, 2023 at 01:41:14PM +0800, Richard Zhu wrote:
> > Add i.MX8MM PCIe EP support.
> >
> > Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
> > ---
> >  arch/arm64/boot/dts/freescale/imx8mm.dtsi | 20 ++++++++++++++++++++
> >  1 file changed, 20 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
> > index 4ee89fdcf59b..8124761f629c 100644
> > --- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi
> > +++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
> > @@ -1293,6 +1293,26 @@ pcie0: pcie@33800000 {
> >                       status = "disabled";
> >               };
> >
> > +             pcie0_ep: pcie_ep@33800000 {
>
> Hyphen is more preferable than underscore in name node.
>
> I fixed it (and the other two patches) up, and applied all DTS patches.

Dropped them, as I just noticed there is v6 of DTS patches being discussed.

Shawn
diff mbox series

Patch

diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
index 4ee89fdcf59b..8124761f629c 100644
--- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
@@ -1293,6 +1293,26 @@  pcie0: pcie@33800000 {
 			status = "disabled";
 		};
 
+		pcie0_ep: pcie_ep@33800000 {
+			compatible = "fsl,imx8mm-pcie-ep";
+			reg = <0x33800000 0x400000>,
+			      <0x18000000 0x8000000>;
+			reg-names = "regs", "addr_space";
+			num-lanes = <1>;
+			interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "dma";
+			fsl,max-link-speed = <2>;
+			power-domains = <&pgc_pcie>;
+			resets = <&src IMX8MQ_RESET_PCIE_CTRL_APPS_EN>,
+				 <&src IMX8MQ_RESET_PCIE_CTRL_APPS_TURNOFF>;
+			reset-names = "apps", "turnoff";
+			phys = <&pcie_phy>;
+			phy-names = "pcie-phy";
+			num-ib-windows = <4>;
+			num-ob-windows = <4>;
+			status = "disabled";
+		};
+
 		gpu_3d: gpu@38000000 {
 			compatible = "vivante,gc";
 			reg = <0x38000000 0x8000>;