From patchwork Thu Dec 15 17:32:33 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lizhi Hou X-Patchwork-Id: 33770 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:e747:0:0:0:0:0 with SMTP id c7csp506211wrn; Thu, 15 Dec 2022 09:42:35 -0800 (PST) X-Google-Smtp-Source: AMrXdXsH/yMNv9XRcOoIOHb6NNrkFFqFFxxzmlq2K1gAf9CEjoo0Kk03M+JR/AlTwxiL34vpx2OZ X-Received: by 2002:a17:90a:4b8b:b0:223:88c9:b17 with SMTP id i11-20020a17090a4b8b00b0022388c90b17mr177867pjh.9.1671126154661; Thu, 15 Dec 2022 09:42:34 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1671126154; cv=pass; d=google.com; s=arc-20160816; b=CyM6W9W5uw28pAF2mIkM2PN+3JOIR/92gsIOJ+61XmBGb+n9Sfl5/HOK9l87P/Ut12 gK0cMME7S0cHplWXODdNWWb5aCMi+IwrYLLNANYUk97yURZyLLgi3s90EWkRiprzpnnE fsSXhzjWoA2lTN8k/0chCX/JKQFOsLGw8Zxm90ZbX0L19l2tfbAQGCYKHaQBx4RY2Ooz ZAprvdAuob5m/7XKbuUEZMTPHz5C3F0mE9NbX8B30wfac+88NEFmtvSmqHT1aOY9riZt k4dlP13w7RU/2XyO9Inj9Ym79Qa64XukLfl1YrjBSErDOxG1pUVCfOXt9Zx6YjUU+aaD TRhg== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=qAzsiTpdL0SBjzJLE5CDWwht36IIvxDx+Yrel2ix04A=; b=Apqt+rgtQuJVvlk6a4Fd4kXq6V2etfZi6OmI5TjeedXZEPaUICx4mfAgrT0iHgkWP7 F8Eo7/lbt0xizPowxa73Irzx6NZ/NCXP9NAVgOPFsWvhBpviA4gKFZx7qb0AtepCPj34 s1P3KimoYU0MDfr5+ZM9jL8dMl/BLxz1qV6/y+cZiCfxC6kkkxUTTnhwu215wCT0fTK+ Cd0wMj6nuL1PYEy0umqeaoBz5OlzD4QHd84K0rWKnX+zHU21DUxhXAzXoAWkpH35fSgt AKQaXTevNbtcFEasplwnhW/itOlqzf7Ou5wY3JHuE8J6fGFSajM6oM8R/L6HMvdNmf0k f8SA== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@amd.com header.s=selector1 header.b=LDCkAMtN; arc=pass (i=1 spf=pass spfdomain=amd.com dmarc=pass fromdomain=amd.com); spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=amd.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id j19-20020a63fc13000000b00478fd9b70c9si3058034pgi.520.2022.12.15.09.42.20; Thu, 15 Dec 2022 09:42:34 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@amd.com header.s=selector1 header.b=LDCkAMtN; arc=pass (i=1 spf=pass spfdomain=amd.com dmarc=pass fromdomain=amd.com); spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=amd.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230024AbiLORc7 (ORCPT + 99 others); Thu, 15 Dec 2022 12:32:59 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48292 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229770AbiLORcx (ORCPT ); Thu, 15 Dec 2022 12:32:53 -0500 Received: from NAM04-DM6-obe.outbound.protection.outlook.com (mail-dm6nam04on2049.outbound.protection.outlook.com [40.107.102.49]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 60461DF27; Thu, 15 Dec 2022 09:32:51 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=Oa/KAjBYsGziGjcCCLL8tBAxcHUc/CeK0vDt0oIEwKBSsGMINADFlQb9tf/d07CQp8umjD6F3zkAAu/kRdCtxnCbZT/Ir0FBTNG2f8Rh6QTsDrxtulqhbvGv6/yPIMJ3qLmelj0qXdgd/vIAn4QJmfsnFYQ1plBm3czxYk+CMonYC+jorgKyKjjpIWegMtfe9bKmFpGZ7j4loo7XSqLevKmpxcN2Jsv625acoLGpaB4f9+MhdLnzN1vL73hz8nvMi9NSi1X/Q1S7TpMwkjHUJKfH7oG79smqt3y/xe0A1yffJTqsu60RnxUU7//XTBgi62yF5vm/NFThscSZPTy3NA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=qAzsiTpdL0SBjzJLE5CDWwht36IIvxDx+Yrel2ix04A=; b=kpOJl8XxRSPXz3gDRf1gdKgV9T1cP4hG7feyL33BlwJKH1zvsBVul7fhBqp+9RIPA2lyYTc/fL3XTQWD+WAsk07gx869fUDvT+Cja6wypyt6Pe1M/8s0Z55pY1zyVmWxvlOffHZSy85+TU0kmTQEEOOI4Z00IUqEAa1U71fnLKs2DyzMNH0sYL+ncz3FrmwGwUMlE1nYBX2qqDX1mdo4gz1p8/ACCo0H8GC3d6Q1LNPIBl45bSZYaLrlAiIRNU3PMSOb7cQRFX1HskOMQJ+Pqt/GZGhGzaXw8szra9HZKGizfKgwy1zfAfF3NVEzAL8fmPHTS3JhjXScPE9bmqnDXw== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 165.204.84.17) smtp.rcpttodomain=kernel.org smtp.mailfrom=amd.com; dmarc=pass (p=quarantine sp=quarantine pct=100) action=none header.from=amd.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amd.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=qAzsiTpdL0SBjzJLE5CDWwht36IIvxDx+Yrel2ix04A=; b=LDCkAMtN/FJ341oo2p5YlWKG/zQH/KomHYW1D4qMG/huFhp7LmXjcbitkUHZm0ZYOisRDr2ABhUUEhlPkVtD1cPzZe/FE3VEM6yL0uXtjQFWg0qfUy0Loiod1BFju0JINdzveX6VuHJDAFIDg+G1wLJKz3mIhkYxZZqIRlNRsj0= Received: from MW4PR03CA0355.namprd03.prod.outlook.com (2603:10b6:303:dc::30) by PH7PR12MB6000.namprd12.prod.outlook.com (2603:10b6:510:1dc::15) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5924.12; Thu, 15 Dec 2022 17:32:49 +0000 Received: from CO1NAM11FT087.eop-nam11.prod.protection.outlook.com (2603:10b6:303:dc:cafe::3) by MW4PR03CA0355.outlook.office365.com (2603:10b6:303:dc::30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5924.14 via Frontend Transport; Thu, 15 Dec 2022 17:32:48 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB03.amd.com; pr=C Received: from SATLEXMB03.amd.com (165.204.84.17) by CO1NAM11FT087.mail.protection.outlook.com (10.13.174.68) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.5924.12 via Frontend Transport; Thu, 15 Dec 2022 17:32:48 +0000 Received: from SATLEXMB03.amd.com (10.181.40.144) by SATLEXMB03.amd.com (10.181.40.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.34; Thu, 15 Dec 2022 11:32:47 -0600 Received: from xsjlizhih40.xilinx.com (10.180.168.240) by SATLEXMB03.amd.com (10.181.40.144) with Microsoft SMTP Server id 15.1.2375.34 via Frontend Transport; Thu, 15 Dec 2022 11:32:47 -0600 From: Lizhi Hou To: , , CC: Lizhi Hou , , , , , Subject: [PATCH V11 XDMA 2/2] dmaengine: xilinx: xdma: Add user logic interrupt support Date: Thu, 15 Dec 2022 09:32:33 -0800 Message-ID: <1671125553-57707-3-git-send-email-lizhi.hou@amd.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1671125553-57707-1-git-send-email-lizhi.hou@amd.com> References: <1671125553-57707-1-git-send-email-lizhi.hou@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1NAM11FT087:EE_|PH7PR12MB6000:EE_ X-MS-Office365-Filtering-Correlation-Id: 6a0c9d9a-7f82-433c-3b01-08dadec262ca X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: MR1uq1bEmp7c34z5is36tuZHzUSJMhhyTZPg7pWYeA4qDNMlM5cI3zh0aF95rdQ+RuTBnGsIUeH3ytktzZYd9CYcwp9guAbLfgc5UMOdsMqjTRuEfswvuzA6HIEVY17OR1JKzJNfWBXTT1sC6GzHEYQsAxwAR6UyYKfymevrCyfQfPToK1alXLp35AOYZwTgx8mXULVI5Wq00SE/WMB5toteg9hTDGD8txTPqKDJMJbFlK9XO10b/ERFOx2L07ng4CpTu/oojJ2s8xms/pvTj+kvsMB2kgL2gtUQuow1+6h0AaNf0J2RXTWa2wquTpyjbb+EnXxbt+zF3KeTSxyKi8agNDVCSEJLkrm3KR4TpPmWkcs5A/8BJejMkXY6WVF7sNCLO+Zoh8CCybOq8XuXb1OTzTA15DAFAgUEJbx8SY7+N5m3lKYkXNRSea+5TS3rlVJ9WdMoMDEnJJSejnaeDiLLZwLBa7yLJmbSD5c9cY/SJ9/LuQ5JHsmFimJCM9klpqUk6HP1wOMTrKllNf/w9xTcbFC9/aLGXdWNNAMmUkFeRfIvml6gLK8lTKCnzpjImY5gkXG4R1PjKnDZhEvnWV+yiVgwYlrCj6n9n2j1MDkWRsSYHKyNom48pVePzmcAshsIx2XPr5UMSxxHfXvmODRgRKjdif/a3C1qy1nSw3rnc5OMsgkMgbKaPZFoyRxTlQftELs5aC1AO9myoPSCfVvKZJdhSsZLElanMPZLYRk= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:CA;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB03.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230022)(4636009)(376002)(39860400002)(396003)(346002)(136003)(451199015)(46966006)(36840700001)(40470700004)(36756003)(356005)(2906002)(82740400003)(81166007)(40480700001)(8936002)(82310400005)(5660300002)(41300700001)(40460700003)(47076005)(426003)(83380400001)(36860700001)(86362001)(478600001)(54906003)(110136005)(44832011)(4326008)(6666004)(70586007)(316002)(8676002)(2616005)(70206006)(26005)(186003)(336012)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 Dec 2022 17:32:48.7382 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 6a0c9d9a-7f82-433c-3b01-08dadec262ca X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT087.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB6000 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1752302778414327290?= X-GMAIL-MSGID: =?utf-8?q?1752302778414327290?= The Xilinx DMA/Bridge Subsystem for PCIe (XDMA) provides up to 16 user interrupt wires to user logic that generate interrupts to the host. This patch adds APIs to enable/disable user logic interrupt for a given interrupt wire index. Signed-off-by: Lizhi Hou Signed-off-by: Sonal Santan Signed-off-by: Max Zhen Signed-off-by: Brian Xu Tested-by: Martin Tuma --- MAINTAINERS | 1 + drivers/dma/xilinx/xdma.c | 85 ++++++++++++++++++++++++++++++++++++ include/linux/dma/amd_xdma.h | 16 +++++++ 3 files changed, 102 insertions(+) create mode 100644 include/linux/dma/amd_xdma.h diff --git a/MAINTAINERS b/MAINTAINERS index d598c4e23901..eaf6590dda19 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -22583,6 +22583,7 @@ L: dmaengine@vger.kernel.org S: Supported F: drivers/dma/xilinx/xdma-regs.h F: drivers/dma/xilinx/xdma.c +F: include/linux/dma/amd_xdma.h F: include/linux/platform_data/amd_xdma.h XILINX ZYNQMP DPDMA DRIVER diff --git a/drivers/dma/xilinx/xdma.c b/drivers/dma/xilinx/xdma.c index 118528295fb7..846f10317bba 100644 --- a/drivers/dma/xilinx/xdma.c +++ b/drivers/dma/xilinx/xdma.c @@ -25,6 +25,7 @@ #include #include #include +#include #include #include #include @@ -713,6 +714,7 @@ static int xdma_set_vector_reg(struct xdma_device *xdev, u32 vec_tbl_start, static int xdma_irq_init(struct xdma_device *xdev) { u32 irq = xdev->irq_start; + u32 user_irq_start; int i, j, ret; /* return failure if there are not enough IRQs */ @@ -755,6 +757,18 @@ static int xdma_irq_init(struct xdma_device *xdev) goto failed_init_c2h; } + /* config user IRQ registers if needed */ + user_irq_start = XDMA_CHAN_NUM(xdev); + if (xdev->irq_num > user_irq_start) { + ret = xdma_set_vector_reg(xdev, XDMA_IRQ_USER_VEC_NUM, + user_irq_start, + xdev->irq_num - user_irq_start); + if (ret) { + xdma_err(xdev, "failed to set user vectors: %d", ret); + goto failed_init_c2h; + } + } + /* enable interrupt */ ret = xdma_write_reg(xdev, XDMA_IRQ_BASE, XDMA_IRQ_CHAN_INT_EN_W1S, ~0); if (ret) @@ -780,6 +794,77 @@ static bool xdma_filter_fn(struct dma_chan *chan, void *param) return chan_info->dir == xdma_chan->dir; } +/** + * xdma_disable_user_irq - Disable user interrupt + * @pdev: Pointer to the platform_device structure + * @irq_num: System IRQ number + */ +void xdma_disable_user_irq(struct platform_device *pdev, u32 irq_num) +{ + struct xdma_device *xdev = platform_get_drvdata(pdev); + u32 user_irq_index; + + user_irq_index = irq_num - xdev->irq_start; + if (user_irq_index < XDMA_CHAN_NUM(xdev) || + user_irq_index >= xdev->irq_num) { + xdma_err(xdev, "invalid user irq number"); + return; + } + user_irq_index -= XDMA_CHAN_NUM(xdev); + + xdma_write_reg(xdev, XDMA_IRQ_BASE, XDMA_IRQ_USER_INT_EN_W1C, + (1 << user_irq_index)); +} +EXPORT_SYMBOL(xdma_disable_user_irq); + +/** + * xdma_enable_user_irq - Enable user logic interrupt + * @pdev: Pointer to the platform_device structure + * @irq_num: System IRQ number + */ +int xdma_enable_user_irq(struct platform_device *pdev, u32 irq_num) +{ + struct xdma_device *xdev = platform_get_drvdata(pdev); + u32 user_irq_index; + int ret; + + user_irq_index = irq_num - xdev->irq_start; + if (user_irq_index < XDMA_CHAN_NUM(xdev) || + user_irq_index >= xdev->irq_num) { + xdma_err(xdev, "invalid user irq number"); + return -EINVAL; + } + user_irq_index -= XDMA_CHAN_NUM(xdev); + + ret = xdma_write_reg(xdev, XDMA_IRQ_BASE, XDMA_IRQ_USER_INT_EN_W1S, + (1 << user_irq_index)); + if (ret) + return ret; + + return 0; +} +EXPORT_SYMBOL(xdma_enable_user_irq); + +/** + * xdma_get_user_irq - Get system IRQ number + * @pdev: Pointer to the platform_device structure + * @user_irq_index: User logic IRQ wire index + * + * Return: The system IRQ number allocated for the given wire index. + */ +int xdma_get_user_irq(struct platform_device *pdev, u32 user_irq_index) +{ + struct xdma_device *xdev = platform_get_drvdata(pdev); + + if (XDMA_CHAN_NUM(xdev) + user_irq_index >= xdev->irq_num) { + xdma_err(xdev, "invalid user irq index"); + return -EINVAL; + } + + return xdev->irq_start + XDMA_CHAN_NUM(xdev) + user_irq_index; +} +EXPORT_SYMBOL(xdma_get_user_irq); + /** * xdma_remove - Driver remove function * @pdev: Pointer to the platform_device structure diff --git a/include/linux/dma/amd_xdma.h b/include/linux/dma/amd_xdma.h new file mode 100644 index 000000000000..ceba69ed7cb4 --- /dev/null +++ b/include/linux/dma/amd_xdma.h @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Copyright (C) 2022, Advanced Micro Devices, Inc. + */ + +#ifndef _DMAENGINE_AMD_XDMA_H +#define _DMAENGINE_AMD_XDMA_H + +#include +#include + +int xdma_enable_user_irq(struct platform_device *pdev, u32 irq_num); +void xdma_disable_user_irq(struct platform_device *pdev, u32 irq_num); +int xdma_get_user_irq(struct platform_device *pdev, u32 user_irq_index); + +#endif /* _DMAENGINE_AMD_XDMA_H */