diff mbox series

[tip:,x86/apic] dt-bindings: x86: apic: Introduce new optional bool property for lapic

Message ID 166998983993.4906.3074674764241043132.tip-bot2@tip-bot2
State New
Headers
Series [tip:,x86/apic] dt-bindings: x86: apic: Introduce new optional bool property for lapic |

Commit Message

tip-bot2 for Thomas Gleixner Dec. 2, 2022, 2:03 p.m. UTC 
  The following commit has been merged into the x86/apic branch of tip:

Commit-ID:     b3a9801cccefda304263b4e84e9dfe49057f3c29
Gitweb:        https://git.kernel.org/tip/b3a9801cccefda304263b4e84e9dfe49057f3c29
Author:        Rahul Tanwar <rtanwar@maxlinear.com>
AuthorDate:    Thu, 24 Nov 2022 16:41:41 +08:00
Committer:     Thomas Gleixner <tglx@linutronix.de>
CommitterDate: Fri, 02 Dec 2022 14:57:14 +01:00

dt-bindings: x86: apic: Introduce new optional bool property for lapic

X86 defines a few possible interrupt delivery modes. With respect to
boot/init time, mainly two interrupt delivery modes are possible.

 - PIC Mode: Legacy external 8259 compliant PIC interrupt controller
 - Virtual Wire Mode: Use lapic as virtual wire interrupt delivery mode

ACPI and MPS spec compliant systems provide this information, but for OF
based systems, it is by default set to PIC mode.

In fact it is hardcoded to legacy PIC mode for OF based x86 systems with no
option to choose the configuration between PIC mode & virtual wire mode.

For this purpose, introduce a new boolean property for the lapic interrupt
controller node which allows to configure it for virtual wire mode as well.

Property name: 'intel,virtual-wire-mode'
Type: Boolean

If not present/not defined, interrupt delivery mode defaults to legacy PIC
mode. If present/defined, interrupt delivery mode is set to virtual wire
mode.

Suggested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Rahul Tanwar <rtanwar@maxlinear.com>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20221124084143.21841-3-rtanwar@maxlinear.com

---
 Documentation/devicetree/bindings/interrupt-controller/intel,ce4100-lapic.yaml | 14 ++++++++++++++
 1 file changed, 14 insertions(+)
diff mbox series

Patch

diff --git a/Documentation/devicetree/bindings/interrupt-controller/intel,ce4100-lapic.yaml b/Documentation/devicetree/bindings/interrupt-controller/intel,ce4100-lapic.yaml
index 55184cb..d2d0145 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/intel,ce4100-lapic.yaml
+++ b/Documentation/devicetree/bindings/interrupt-controller/intel,ce4100-lapic.yaml
@@ -39,6 +39,19 @@  properties:
   '#interrupt-cells':
     const: 2
 
+  intel,virtual-wire-mode:
+    description: Intel defines a few possible interrupt delivery
+      modes. With respect to boot/init time, mainly two interrupt
+      delivery modes are possible.
+      PIC Mode - Legacy external 8259 compliant PIC interrupt controller.
+      Virtual Wire Mode - use lapic as virtual wire interrupt delivery mode.
+      For ACPI or MPS spec compliant systems, it is figured out by some read
+      only bit field/s available in their respective defined data structures.
+      For OF based systems, it is by default set to PIC mode.
+      But if this optional boolean property is set, then the interrupt delivery
+      mode is configured to virtual wire compatibility mode.
+    type: boolean
+
 required:
   - compatible
   - reg
@@ -54,4 +67,5 @@  examples:
         reg = <0xfee00000 0x1000>;
         interrupt-controller;
         #interrupt-cells = <2>;
+        intel,virtual-wire-mode;
     };