From patchwork Mon Nov 28 11:53:54 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: tip-bot2 for Thomas Gleixner X-Patchwork-Id: 26682 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:f944:0:0:0:0:0 with SMTP id q4csp5609626wrr; Mon, 28 Nov 2022 04:03:56 -0800 (PST) X-Google-Smtp-Source: AA0mqf7d74M3I4X3ixXHOftAHVzSA4wmKUaFQ6TU9qPohgpJBXwJPRiidqEriLzN9WZxLyVIjx8k X-Received: by 2002:a17:90a:5801:b0:218:90b5:d1f2 with SMTP id h1-20020a17090a580100b0021890b5d1f2mr45594919pji.142.1669637036030; Mon, 28 Nov 2022 04:03:56 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1669637036; cv=none; d=google.com; s=arc-20160816; b=fqun4gPxUo1qCXli8YspMX9ckYuZjqKs8bzX3lpmExokciEKKamPaBhzSYrxdbGCSd uoUWQYlpkeNgi/pAM/SVZq+Ggpvn/wkIGMi4lVSpK/RQ0du2JkNYgfDvw7ZcGgLNu1o5 Q4yAQgNBvHquo5o6bVZ1b3pZrPMreeIJpzUeqdQvINnnNVXiGGp9oYpCtpWqOc2zsN6X EGDEX+lkFN4msrKBkB1Dn6Moh3e1Rkx99oNmoZkEQomyC8OEwPtoc0LB/oJGtFfthNE7 O7l78TfKeqDrViUMQFoXjTlIzZd5/mBmOhUxPvrBHlsxWGCpWEVn7foSfw2zRIxCu3+R M40A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:robot-unsubscribe :robot-id:message-id:mime-version:references:in-reply-to:cc:subject :to:reply-to:sender:from:dkim-signature:dkim-signature:date; bh=ytrbYY9Bi5wFxKoqsejNQD9YZToZ4Kc9rbTdTcNgoK0=; b=b8C2ZzkUDrclSQZDuSJRLU8suGBbE3lQPSer7bXdq/1vZuLjPXYbKdiRF+dphMNsgE sW0hRJiCbw2jkihip9fhbZErBZrZo3jmFfW6A01ZLq3ZIhMAV6imdLhx2oSGXcRNZVA2 5UaQx+VOrihue2Q9cgVNc5AsAKfIyQS0Z0NiJiDJ5QG5qr1nV6iWkeODUlyud44KbkbU 0K63wiakw1VupdSXOIAlhJ9NOqSoCbYnfREaJAUlzF6XGEEwypmqeey8Tt8+oTXQQZHk kMAjHkjLhlP3Ra+klpErBakfy6BMUUvz4lmAJab/d+Ye1vXQwqa/ADZGN/xh+N2Q1a3W bhDg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=gjQIXkKb; dkim=neutral (no key) header.i=@linutronix.de header.s=2020e header.b="/YX0mhss"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id x2-20020a056a00188200b00573f637f587si12412583pfh.227.2022.11.28.04.03.38; Mon, 28 Nov 2022 04:03:56 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=gjQIXkKb; dkim=neutral (no key) header.i=@linutronix.de header.s=2020e header.b="/YX0mhss"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231307AbiK1LyC (ORCPT + 99 others); Mon, 28 Nov 2022 06:54:02 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59256 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230389AbiK1Lx6 (ORCPT ); Mon, 28 Nov 2022 06:53:58 -0500 Received: from galois.linutronix.de (Galois.linutronix.de [IPv6:2a0a:51c0:0:12e:550::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7CB4CB1CC for ; Mon, 28 Nov 2022 03:53:57 -0800 (PST) Date: Mon, 28 Nov 2022 11:53:54 -0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1669636435; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=ytrbYY9Bi5wFxKoqsejNQD9YZToZ4Kc9rbTdTcNgoK0=; b=gjQIXkKbeKAYu/10hwabYJdkI5yaNILG6jrcaMwwI712wPNUY6d6OtkrdFhSB4Rzyj2+4x D2LFTvzzVTT6ZCuWhF9fam0O9jYbSEvZMSJFGKOXELk42DhYELfyiyE7cJQ3YSbSEKCUh8 yeWqE5OVR6+pOPYH9925g5MliEBRCIFw1kldH5muoFgF7zRYV/+hZQC3agRMWuob17K6Nf JU8BFbLbf80JJricw8615/AT4ezNX0xixH8CUX+Tg504uxFKhSRPIx3e/KHFH1C09NUhKb VXl78ISBXWiDbdAABSPzDBAH9zdSZdWjTQtRLBLU1pyV2TY3qul+JC1VYKsXlQ== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1669636435; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=ytrbYY9Bi5wFxKoqsejNQD9YZToZ4Kc9rbTdTcNgoK0=; b=/YX0mhsszyxHOew4p0Kt2Si4LDxZ+Q3uCikhxZz3qidNifNbZf/bYjcRsS+FBEXV3dAfb0 qBdOttXSIhW3BHAg== From: "irqchip-bot for AngeloGioacchino Del Regno" Sender: tip-bot2@linutronix.de Reply-to: linux-kernel@vger.kernel.org To: linux-kernel@vger.kernel.org Subject: [irqchip: irq/irqchip-next] irqchip/irq-mtk-cirq: Add support for System CIRQ on MT8192 Cc: AngeloGioacchino Del Regno , Marc Zyngier , tglx@linutronix.de In-Reply-To: <20221128092217.36552-5-angelogioacchino.delregno@collabora.com> References: <20221128092217.36552-5-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 Message-ID: <166963643407.4906.7778593583371085086.tip-bot2@tip-bot2> Robot-ID: Robot-Unsubscribe: Contact to get blacklisted from these emails X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED,SPF_HELO_NONE, SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1750741324366619894?= X-GMAIL-MSGID: =?utf-8?q?1750741324366619894?= The following commit has been merged into the irq/irqchip-next branch of irqchip: Commit-ID: 5c4e0aac0b2a27168844da49cee2c5dff2925d22 Gitweb: https://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms/5c4e0aac0b2a27168844da49cee2c5dff2925d22 Author: AngeloGioacchino Del Regno AuthorDate: Mon, 28 Nov 2022 10:22:17 +01:00 Committer: Marc Zyngier CommitterDate: Mon, 28 Nov 2022 11:44:02 irqchip/irq-mtk-cirq: Add support for System CIRQ on MT8192 On some SoCs the System CIRQ register layout is slightly different, as there are more registers per function and in some cases other differences later in the layout: this is seen on at least MT8192, but it's also valid for some other "contemporary" SoCs both for Chromebooks and for smartphones. Add the new "v2" register layout and use it if the compatible "mediatek,mt8192-cirq" is found. Signed-off-by: AngeloGioacchino Del Regno Signed-off-by: Marc Zyngier Link: https://lore.kernel.org/r/20221128092217.36552-5-angelogioacchino.delregno@collabora.com --- drivers/irqchip/irq-mtk-cirq.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/drivers/irqchip/irq-mtk-cirq.c b/drivers/irqchip/irq-mtk-cirq.c index 4776ed6..76bc028 100644 --- a/drivers/irqchip/irq-mtk-cirq.c +++ b/drivers/irqchip/irq-mtk-cirq.c @@ -39,6 +39,18 @@ static const u32 mtk_cirq_regoffs_v1[] = { [CIRQ_CONTROL] = 0x300, }; +static const u32 mtk_cirq_regoffs_v2[] = { + [CIRQ_STA] = 0x0, + [CIRQ_ACK] = 0x80, + [CIRQ_MASK_SET] = 0x180, + [CIRQ_MASK_CLR] = 0x200, + [CIRQ_SENS_SET] = 0x300, + [CIRQ_SENS_CLR] = 0x380, + [CIRQ_POL_SET] = 0x480, + [CIRQ_POL_CLR] = 0x500, + [CIRQ_CONTROL] = 0x600, +}; + #define CIRQ_EN 0x1 #define CIRQ_EDGE 0x2 #define CIRQ_FLUSH 0x4 @@ -277,6 +289,7 @@ static const struct of_device_id mtk_cirq_of_match[] = { { .compatible = "mediatek,mt2701-cirq", .data = &mtk_cirq_regoffs_v1 }, { .compatible = "mediatek,mt8135-cirq", .data = &mtk_cirq_regoffs_v1 }, { .compatible = "mediatek,mt8173-cirq", .data = &mtk_cirq_regoffs_v1 }, + { .compatible = "mediatek,mt8192-cirq", .data = &mtk_cirq_regoffs_v2 }, { /* sentinel */ } };